ZR36067 データシートの表示（PDF） - Unspecified

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ZR36067

AV PCI CONTROLLER

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AV PCI CONTROLLER

such write cycles[2]. The second is a GO command to the

ZR36050 (configured a priori as one of the guests) in JPEG

mode; the same type of bus cycle can be used to toggle the

START pin of the ZR36060. The third is a PostOffice cycle, initi-

ated by the host software, targeted to any one of the eight

guests; in particular, PostOffice cycles are used to program the

ZR36060, or the ZR36050 and ZR36016.

5.3.1 Flexible GuestBus Timing

Different guest devices may have different bus timing require-

ments. In order to meet these requirements and still master the

GuestBus efficiently, the ZR36067 has two timing parameters

for each guest:

TgdurN is the duration of a GWR or GRD signal when accessing

guest N.

TgrecN is the minimum recovery time in which GRD and GWR

must be non active after the rising edge of the previous access

(read or write) to guest N.

Tgdur and Tgrec are configured by the host in units of PCI clock

(3,4,12 or 15 PCI clocks are the possible values).

Additional timing parameters are given in section 15.0 “AC

Timing Specifications”.

5.3.2 Code-Write Operations

Code-Write cycles are initiated by the GuestBus master if all of

the conditions below are met:

• The CFIFO is not empty.

• A PostOffice request is not pending.

• The GRDY input is high (‘1’).

A code-write cycle consists of reading one code byte from the

CFIFO and writing it to the guest selected by the host for code-

write cycles, to the register address configured by the host. The

timing parameters of the code-write cycle are those pro-

grammed by the host for this specific guest device. Note that the

same parameters apply for PostOffice accesses to this guest.

5.3.3 Doubleword to Bytes Mapping in Code-Write

Operations

The code is read in doublewords from main memory, and trans-

ferred in bytes to the guest device. The ordering of the bytes is

such that the least significant byte of the doubleword is the first

one to be sent over the GuestBus, and the most significant byte

is the last one.

(PODir). The identity of the targeted guest and its specific

register are also specified by the PostOffice register. In both

read and write cycles the timing parameters of the cycle are

those configured by the host for the targeted guest. Upon com-

pletion of a PostOffice cycle, the pending bit is reset to ‘0’ by the

ZR36067.

PostOffice Write: The GuestBus master transfers the least sig-

nificant 8 bits of the PostOffice register out on the bus.

PostOffice Read: The GuestBus master reads from the specified

target and writes the input byte into the least significant 8 bits of

the PostOffice register (POData)

5.3.5 GuestBus Wait States

Slow guests that are equipped with a “bus hold” output can force

a code-write or PostOffice GuestBus cycle to be extended by

one or more additional PCI clocks, by asserting the GWS signal.

GWS is first sampled with the PCI clock that precedes the one

that triggers the de-assertion of GWR or GRD (if Tgdur of the

accessed guest is M PCI clocks, GWS is sampled M-1 clocks

after the assertion of GWR or GRD). When GWS is sampled

high again, the cycle is completed.

Insertion of wait states is possible during both code-write and

PostOffice cycles.

The maximum number of PCI clock cycles allowed for GRD or

GWR, including wait-states, is 64. If a guest holds the cycle until

this limit expires, the GuestBus master aborts the cycle. If the

cycle was a PostOffice one, the PostOffice time-out bit of the

PostOffice register is set to ‘1’, and the PostOffice pending bit is

cleared. If the cycle was a code-write (or code-read, if viewed

from the PCI side), the code-write time-out flag (CodTime) is set

to ‘1’.

Figure shows two examples of GuestBus cycles. The upper one

is a write to guest 0, register 0, followed by a read from guest 0,

register 5. Note that for guest 0 Tgdur0=3 and Tgrec0=4. The lower

example shows a read from guest 2, register 1, with 3 wait-states

inserted by the guest.

Notice that the assertions of GADR and GCS are done together.

The assertion of GRD and GWR is done one PCI clock after the

assertion of GADR and GCS. The de-assertion of GRD and

GWR is done one PCI clock before the de-assertion of GADR

and GCS.

5.3.4 PostOffice Operations

When the PostOffice pending bit (POPen) in the PostOffice

register is set to ‘1’, the GuestBus master completes the current

code-write cycle (if such is executed), and executes a PostOffice

cycle, even when the Code FIFO is not empty. The type of the

cycle (read or write) is determined by the PostOffice direction bit

2. A typical choice for guest configured a priori for the code-write cycles would be a decompression device, such as the ZR36110 or ZR36700, in the ZR36067’s MPEG

mode.

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