ZR36067 データシートの表示（PDF） - Unspecified

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ZR36067

AV PCI CONTROLLER

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AV PCI CONTROLLER

software is allowed to set those bits only while the ZR36067 is

the sync master.

When VFIFO_FB is set, if the Video FIFO is close to overflow

status, PXEN is de-asserted to hold the ZR36060 video output

until the Video FIFO is emptied. When CFIFO_FB is set, if the

Code FIFO underflows, and CBUSY is asserted, PXEN is de-

asserted to hold the ZR36060 video output until the Code FIFO

is filled. When RTBSY_FB is set, if RTBSY is asserted by the

ZR36060 during the active portion of the field, PXEN is de-

asserted until RTBSY is de-asserted.

5.2.3.3 RTBSY Signal Control

The ZR36067’s RTBSY input is connected to the ZR36060’s

RTBSY output. The ZR36067 uses RTBSY to detect overflow

and underflow conditions in the ZR36060 strip memory.

In Motion Video Compression mode, if RTBSY is asserted when

the first active pixel of a line is sampled, a condition that indi-

cates a strip buffer overflow, the ZR36067 abandons the

compression process for the field and waits for the beginning of

the following field.

In Motion Video Decompression mode, de-assertion of RTBSY

is used to decide when to initiate the decompression process.

In all modes, when RTBSY_FB is set, RTBSY is checked by the

ZR36067 at the following times:

• Before the trailing edge of VSYNC, which triggers the start of

a new field process in the ZR36060,

• During the active portion of the field.

The ZR36067 de-asserts PXEN if RTBSY is asserted at those

times. PXEN is asserted again after RTBSY is de-asserted.

5.2.4 Pixel Transfer In Still Image Compression Mode

The image is transferred by the host software to the ZR36067’s

extended 24-bit video bus. The host writes the pixels one by one

to a dedicated register (the Still Transfer register) in the

ZR36067. Each pixel is synchronized with the video clock and

transferred to the Video Interface port.

Two modes of host access are supported:

• The host verifies, by polling, the availability of the Still Trans-

fer register before each pixel write access. Typically, this

mode would be used after writing the first pixel of each line,

before writing the remainder of the line.

• The host configures the WaitState parameter and writes the

pixels continuously to the Still Transfer register. The

ZR36067 de-asserts the PCI TRDY signal every host access

with the timing specified by the WaitState parameter. Typi-

cally, this mode would be used to transfer the pixels of a line

after the first.

The Still Transfer write protocol and the associated internal

mechanism of the ZR36067 are described below:

• The host writes a pixel using a single data phase memory

write cycle. The pixel is latched in the Still Transfer register

using the PCI clock.

• The Still_Bsy bit is set.

• The incoming pixel is synchronized with the Video Interface

clock. The PXEN output signal is asserted and the pixel is

driven out on the correct video clock phase.

• Feedback from the Video Interface resets the Still_Bsy bit,

indicating that the video port is empty and the following host

write is permitted.

5.2.5 Pixel Transfer In Still Image Decompression Mode

The image is transferred from the ZR36067’s extended 24-bit

video bus to system memory. The host software reads the pixels

one by one from the Still Transfer register. After each pixel is

fetched from the video port, it is synchronized with the PCI clock,

ready to be read by the software.

Before each read access, the host software should check the

Still_Bsy bit to verify availability of data in the register. The

register contents are valid only if the Still_Bsy bit is 0. Note that

by configuring the WaitState parameter, it is possible to ensure

that the Still Transfer register will be valid every read access,

making it unnecessary to check the Still_Bsy bit.

The protocol for a still image decompression read operation, and

the ZR36067’s behavior, are as follows:

• The ZR36067 checks the Still_Bsy bit. If it is 1, meaning that

the previous valid pixel was read by the host, the ZR36067

fetches a new pixel from the ZR36016.

• PXEN is asserted, causing a new pixel to be driven onto the

video bus.

• The new pixel is synchronized with the PCI clock and

latched in the Still Transfer register.

• Still_Bsy is reset to 0, to indicate that a new valid pixel is

available.

• The host software reads the pixel by means of a memory

read access to the Still Transfer register, and Still_Bsy is set

to 1.

5.3 GuestBus Interface

The ZR36067 masters a generic MCU-style bus intended to con-

currently host up to eight slave devices (referred to as “guests”).

The bus consists of 8 data lines (GDAT[7:0]), 3 address lines

(GADR[2:0]), 8 active-low chip-select lines (GCS[7:0]), read and

write signals (GRD, GWR), and a wait-state insertion line

(GWS). The bus also includes two interrupt-request inputs

(GIRQ[1:0]) and one status/acknowledge input (GRDY). Three

types of data transfers are possible on the guest bus. One is a

code-write cycle, initiated by the code DMA controller of the

ZR36067, targeted to one of the guests, configured a-priori for

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