H27UBG8T2BTA データシートの表示（PDF） - Hynix Semiconductor
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H27UBG8T2BTA Datasheet PDF : 57 Pages
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Preliminary
H27UBG8T2BTR-BC Series
32Gb(4096M x 8bit) Legacy MLC NAND Flash
Notes:
1. Random Data Input/Output must be performed in a selected page.
2. Any command between 11h and 81h is prohibited except 70h, 78h, 75h and FFh.
3. Multi-plane Random data-out must be used after multi plane read operations
(Multi Plane Page Read, Multi Plane Cache Read and Multi Plane Read for Copy Back).
4. Do not change plane address order when using all MULTI-PLANE operations.
5. All cache operation (cache program, cache read) is available only within a block.
6. It‟s possible to confirm the multi-plane cache read first step using both 30h and 33h.
Caution:
1. Any undefined command inputs are prohibited except for above command set.
2. Multi plane page read, multi plane cache read, and multi plane read for copy-back must be used
after Multi plane programmed page, multi plane cache program, and multi plane copy-back program.
1.9. Mode Selection
CLE
ALE
CE# WE# RE# WP#
MODE
H
L
L
L
H
L
H
X
Command Input
Read Mode
H
X
Address Input ( 5 Cycles )
H
L
L
L
H1)
L
H
H
Command Input
Write Mode
H
H
Address Input ( 5 Cycles )
L
L
L
H
H Data Input
L
L 1)
L
H
X Sequential Read and Data Output
X
X
X
H 3)
H 3)
X During Read (Busy)
X
X1)
X
X
X
H During Program (Busy)
X
X
X
X
X
H During Erase (Busy)
X
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/Vcc2) Stand-By
Notes:
1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. WE# and RE# during Read Busy must be keep on high to prevent unplanned
command/address/data input or to avert unintended data out. In this time, only Reset,
Read Status, and Multi Plane Read Status can be inputted to the device.
Rev 0.7 / Jan. 2011
13
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