Preliminary
H27UBG8T2BTR-BC Series
32Gb(4096M x 8bit) Legacy MLC NAND Flash
2.8.2. Status Register Coding For 75h command
I/O
Page
Program
Block
Erase
Read
0
/ Fail
/ Fail
N/A
1
Plane 0
Pass / Fail
Plane 0
Pass / Fail
N/A
2
Plane 1
Pass / Fail
Plane 1
Pass / Fail
N/A
3
N/A
N/A
N/A
4
N/A
N/A
N/A
5
N/A
N/A
N/A
6
Ready /
Busy
Ready /
Busy
Ready /
Busy
7
Write
Protect
Write
Protect
Write
Protect
Cache
Read
N/A
N/A
N/A
N/A
N/A
Ready /
Busy
Ready /
Busy
Write
Protect
Cache
Program
Chip
Pass /
Fail (N)
Plane 0
Pass /
Fail (N)
Plane 1
Pass /
Fail (N)
Plane 0
Pass /
Fail (N-1)
Plane 1
Pass /
Fail (N-1)
Ready /
Busy
Ready /
Busy
Write
Protect
Coding
75h
N page
Pass : „0‟ Fail : „1‟
N page
Pass : „0‟ Fail : „1‟
N page
Pass : „0‟ Fail : „1‟
N -1 page
Pass : „0‟ Fail : „1‟
N -1 page
Pass : „0‟ Fail : „1‟
Ready / Busy
Busy : „0‟ Ready : „1‟
Data Cache
Ready / Busy
Busy : „0‟ Ready : „1‟
Protected : „0‟
Not Protected : „1‟
2.9. Device Identifier Coding
Parameter
Device Identifier Byte
1st
2nd
3rd
4th
5th
6th
Symbol
Description
Manufacturer Code
Device Identifier
Internal chip number, cell Type, Number of Simultaneously
Programmed Pages, Interleaved Program, Write Cache.
Page size, Block size, Redundant area size
Plane Number, ECC Level
Technology (Design Rule), , Interface
Rev 0.7 / Jan. 2011
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