VT82C596 データシートの表示（PDF） - Unspecified

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VT82C596

PCI INTEGRATED PERIPHERAL CONTROLLER

Unspecified 

:H &RQQHFW 7HFKQRORJLHV ,QF

VT82C596B

Signal Name

RFSH#

AEN

IRQ0OUT /

GPO14

IRQ1

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8# / GPI6

IRQ9

IRQ10

IRQ11

IRQ12

IRQ14

IRQ15

DRQ7-5, 3-0

DACK7-5, 3-0#

TC

SPKR

ISA Bus Interface (continued)

Pin #

I/O Signal Description

W7

IO Refresh. As an output RFSH# indicates when a refresh cycle is in progress. As an

input RFSH# is driven by 16-bit ISA Bus masters to indicate refresh cycle.

Y4

O Address Enable. AEN is asserted during DMA cycles to prevent I/O slaves from

misinterpreting DMA cycles as valid I/O cycles.

H20

O Multifunction Pin

Rx74[7] = 1 Interrupt Request 0 Output. Reflects the state of the internal

system timer IRQ0 signal.

Rx74[7] = 0 General Purpose Output 14.

J20

I Interrupt Request 1.

T9

I Interrupt Request 3.

W9

I Interrupt Request 4.

U8

I Interrupt Request 5.

V8

I Interrupt Request 6.

Y8

I Interrupt Request 7.

Y20

I Multifunction Pin

Rx5A[2] = 0 Internal RTC disabled. Interrupt Request 8 from external RTC

Rx5A[2] = 1 Internal RTC enabled. General Purpose Input 6.

U1

I Interrupt Request 9.

U12

I Interrupt Request 10.

W13

I Interrupt Request 11.

T13

I Interrupt Request 12.

V14

I Interrupt Request 14.

Y14

I Interrupt Request 15.

U17, U16,

I DMA Request. Used to request DMA services from the internal DMA controller.

Y16, U5, V2,

U6, W15

W17, V16, O Acknowledge. Used by the internal DMA controller to indicate that a request for

T15, V5, Y10,

DMA service has been granted.

W6, U14

V10

O Terminal Count. Asserted to DMA slaves as a terminal count indicator.

K17

O Speaker Drive. The output of internal timer/counter 2.

Revision 0.3 June 17, 1999

-12-

Pinouts

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