VT82C596 データシートの表示（PDF） - Unspecified

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VT82C596

PCI INTEGRATED PERIPHERAL CONTROLLER

Unspecified 

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VT82C596B

Signal Name

PDCS1#

PDCS3#

SDCS1#

SDCS3#

PDA[2-0]

SDA[2-0]

PDD[15-0]

SDD[15-0]

UltraDMA-33 / 66 Enhanced IDE Interface (continued)

Pin #

H17

H16

B18

C18

G17, G18,

G16

A18, B17,

C17

F19, E17,

E19, D17,

D19, C19,

B19, A19,

A20, B20,

C20, D20,

D18, E20,

E18, F20

D15, C15,

A15, E14,

B14, D13,

B13, D12,

C12, A13,

C13, A14,

C14, D14,

B15, E15

I/O Signal Description

O Primary Master Chip Select. This signal corresponds to CS1FX# on the primary

IDE connector.

O Primary Slave Chip Select. This signal corresponds to CS3FX# on the primary

IDE connector.

O Secondary Master Chip Select. This signal corresponds to CS17X# on the

secondary IDE connector.

O Secondary Slave Chip Select. This signal corresponds to CS37X# on the secondary

IDE connector.

O Primary Disk Address. PDA[2:0] are used to indicate which byte in either the ATA

command block or control block is being accessed.

O Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the

ATA command block or control block is being accessed.

IO Primary Disk Data

IO Secondary Disk Data

Revision 0.3 June 17, 1999

-10-

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