ZR36067 データシートの表示（PDF） - Unspecified

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ZR36067

AV PCI CONTROLLER

Unspecified 

AV PCI CONTROLLER

11.0 SUBSYSTEM ID AND SUBSYSTEM VENDOR ID

The Subsystem ID and Subsystem Vendor ID registers are con-

figured at PCI Reset time. Immediately after the trailing edge of

PCIRST, the ZR36067 latches the current state on 32 of its input

pins into these registers. Thus, if the system design takes this

into consideration and ensures that the relevant pins are not

being driven by any other device at the trailing edge of PCIRST,

the required states can be assigned to the pins by means of pull-

up or pull-down resistors.

Note: To ensure that the states of the pins are latched correctly,

they must remain stable for at least 3 PCI clock periods after the

trailing edge of PCIRST.

11.1 Subsystem ID

The pins used to configure the Subsystem ID are shown in Table

12.

Table 12: Signal Pins Used For Subsystem ID

Subsystem ID Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Signal Pin

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

UV/G7

UV/G6

UV/G5

UV/G4

UV/G3

UV/G2

UV/G1

UV/G0

11.2 Subsystem Vendor ID

The pins used to configure the Subsystem Vendor ID are shown

in Table 13.

Table 13: Signal Pins Used For Subsystem Vendor ID

Subsystem Vendor ID Bit Signal Pin

15

GDAT7

14

GDAT6

13

GDAT5

12

GDAT4

11

GDAT3

10

GDAT2

9

GDAT1

8

GDAT0

7

Y/R7

6

Y/R6

5

Y/R5

4

Y/R4

3

Y/R3

2

Y/R2

1

Y/R1

0

Y/R0

23

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