XRT84L38 データシートの表示（PDF） - Exar Corporation
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XRT84L38 Datasheet PDF : 453 Pages
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XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 227
5.1.3.1 T1 RECEIVE INPUT INTERFACE - MVIP 2.048 MHZ.............................................................................................. 227
TABLE 45: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ................................................................................................ 228
FIGURE 49. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING MVIP 2.048MBIT/S DATA BUS................................ 229
FIGURE 50. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT MVIP 2.048MBIT/S ...................................... 229
5.1.3.2 T1 RECEIVE INPUT INTERFACE - 4.096 MHZ ....................................................................................................... 229
TABLE 46: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ................................................................................................ 230
FIGURE 51. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 4.096MBIT/S DATA BUS ......................................... 231
FIGURE 52. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 4.096MBIT/S ................................................ 231
5.1.3.3 T1 RECEIVE INPUT INTERFACE - 8.192 MHZ ....................................................................................................... 231
TABLE 47: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ................................................................................................ 232
FIGURE 53. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 8.192MBIT/S DATA BUS ......................................... 233
FIGURE 54. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 8.192MBIT/S ................................................ 233
5.1.3.4 T1 RECEIVE INPUT INTERFACE - MULTIPLEXED 12.352MBIT/S ............................................................................. 233
FIRST OCTET OF 12.352MBIT/S DATA STREAM.......................................................................................... 234
SECOND OCTET OF 12.352MBIT/S DATA STREAM...................................................................................... 234
THIRD OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 234
SIXTH OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 235
SEVENTH OCTET OF 12.352MBIT/S DATA STREAM .................................................................................... 235
EIGHTH OCTET OF 12.352MBIT/S DATA STREAM ....................................................................................... 235
NINETH OCTET OF 12.352MBIT/S DATA STREAM ....................................................................................... 235
FIGURE 55. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 12.352MBIT/S DATA BUS ....................................... 236
FIGURE 56. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 12.352MBIT/S .............................................. 236
5.1.3.5 T1 RECEIVE INPUT INTERFACE - BIT-MULTIPLEXED 16.384MBIT/S ....................................................................... 236
FIRST OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 237
NINTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 237
TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 237
THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................ 238
FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 238
FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 238
SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM.................................................................................. 238
FIGURE 57. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ....................................... 239
FIGURE 58. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT BIT-MULTIPLEXED 16.384MBIT/S ................... 239
5.1.3.6 T1 RECEIVE INPUT INTERFACE - HMVIP 16.384MBIT/S ....................................................................................... 239
FIRST OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 240
NINTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 240
ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................... 240
THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................ 241
FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 241
TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 241
TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 241
FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 241
SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM.................................................................................. 241
FIGURE 59. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ....................................... 242
FIGURE 60. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT HMVIP 16.384MBIT/S.................................. 243
5.1.3.7 T1 RECEIVE INPUT INTERFACE - H.100 16.384MBIT/S......................................................................................... 243
FIRST OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 243
NINTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 244
ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................... 244
THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................ 244
FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 244
TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 245
TWELFTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 245
FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 245
SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM.................................................................................. 245
FIGURE 61. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING H.100 16.384MBIT/S DATA BUS ............................. 246
FIGURE 62. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT H.100 16.384MBIT/S ................................... 246
6.0 THE E1 TRANSMIT SECTION ............................................................................................................ 247
6.1 THE E1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK............................................................. 247
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