XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.1

6.1.1 DESCRIPTION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK .............................................. 247

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 247

6.1.2 BRIEF DISCUSSION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT XRT84V24

COMPATIBLE 2.048MBIT/S MODE ............................................................................................................................ 248

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................. 248

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 249

6.1.2.1 CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF TRANSMIT

TIMING SOURCE = TXSERCLK_N ............................................................................................................................ 250

FIGURE 63. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH TXSERCLK_N AS TRANSMIT TIMING SOURCE ............. 251

FIGURE 64. WAVEFORMS OF THE SIGNALS THAT CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL

EQUIPMENT WITH THE TRANSMIT SERIAL CLOCK BEING THE TIMING SOURCE OF THE TRANSMIT SECTION ........................ 252

6.1.2.2 CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE TRANSMIT

TIMING SOURCE = OSCCLK .................................................................................................................................. 252

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................. 253

FIGURE 65. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH OSCCLK DRIVEN DIVIDED CLOCK AS TRANSMIT TIMING SOURCE

254

FIGURE 66. WAVERFORMS OF THE SIGNALS CONNECTING THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL

EQUIPMENT WITH THE OSCCLK DRIVEN DIVIDED CLOCK AS THE TIMING SOURCE OF THE TRANSMIT SECTION................. 255

6.1.2.3 CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT FOR LOOP-TIM-

ING APPLICATIONS .................................................................................................................................................. 255

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H) ................................................. 256

FIGURE 67. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH RECOVERED RECEIVE LINE CLOCK AS TRANSMIT TIMING SOURCE

257

FIGURE 68. WAVERFORMS OF THE SIGNALS CONNECTING THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL

EQUIPMENT WITH THE RECOVERED RECEIVE LINE CLOCK BEING THE TIMING SOURCE OF TRANSMIT SECTION ................. 258

6.1.3 BRIEF DISCUSSION OF THE TRANSMIT HIGH-SPEED BACK-PLANE INTERFACE ........................................... 258

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ....................... 258

TRANSMIT MULTIPLEX ENABLE BIT = 0....................................................................................................... 259

TRANSMIT MULTIPLEX ENABLE BIT = 1....................................................................................................... 260

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (NDIRECT ADDRESS = 0XN0H, 0X20H) ......................... 260

6.1.3.1 E1 TRANSMIT INPUT INTERFACE - MVIP 2.048 MHZ ........................................................................................... 260

FIGURE 69. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING MVIP 2.048MBIT/S DATA BUS.................................. 261

FIGURE 70. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT MVIP 2.048MBIT/S........................................ 262

6.1.3.2 E1 TRANSMIT INPUT INTERFACE - 4.096 MHZ ..................................................................................................... 262

FIGURE 71. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 4.096MBIT/S DATA BUS ........................................... 263

FIGURE 72. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 4.096MBIT/S MODE........................................ 263

6.1.3.3 E1 TRANSMIT INPUT INTERFACE - 8.192 MHZ ..................................................................................................... 263

FIGURE 73. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 8.192MBIT/S DATA BUS ........................................... 264

FIGURE 74. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 8.192MBIT/S MODE........................................ 265

6.1.3.4 E1 TRANSMIT INPUT INTERFACE - BIT-MULTIPLEXED 16.384MBIT/S..................................................................... 265

FIRST OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 266

SECOND OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 266

FIFTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 266

SIXTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 266

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM..................................................................................... 266

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 267

FIGURE 75. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ......................................... 268

FIGURE 76. IMING SIGNAL WHEN THE FRAMER IS RUNNING AT BIT-MULTIPLEXED 16.384MBIT/S MODE ............................................ 268

6.1.3.5 E1 TRANSMIT INPUT INTERFACE - HMVIP 16.384MBIT/S..................................................................................... 268

FIRST OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 269

THIRD OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 269

FIFTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 269

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM..................................................................................... 269

SECOND OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 270

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 270

SIXTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 270

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 270

FIGURE 77. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ......................................... 271

FIGURE 78. TIMING SIGNAL WHEN THE FRAMER IS RUNNING AT HMVIP 16.384MBIT/S MODE ......................................................... 271

6.1.3.6 E1 TRANSMIT INPUT INTERFACE - H.100 16.384MBIT/S ...................................................................................... 271

FIRST OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 272

VI

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