XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

XRT84L38

REV. 1.0.1

OCTAL T1/E1/J1 FRAMER

THIRD OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 272

FIFTH OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 272

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 273

SECOND OCTET OF 16.384MBIT/S DATA STREAM...................................................................................... 273

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 273

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 273

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 273

FIGURE 79. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ......................................... 274

FIGURE 80. TIMING SIGNAL WHEN THE FRAMER IS RUNNING AT H.100 16.384MBIT/S MODE ........................................................... 275

6.2 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK................................................................. 275

6.2.1 DESCRIPTION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK............................................. 275

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 276

6.2.2 BRIEF DISCUSSION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK OPERATING AT XRT84V24

COMPATIBLE 2.048MBIT/S MODE ............................................................................................................................ 276

SLIP BUFFER CONTROL REGISTER (SBCR) (INDIRECT ADDRESS = 0XN0H, 0X16H) ................................... 276

SLIP BUFFER CONTROL REGISTER (SBCR) (INDIRECT ADDRESS = 0XN0H, 0X16H) ................................... 277

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 278

6.2.2.1 CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE SLIP

BUFFER IS BYPASSED ............................................................................................................................................. 279

FIGURE 81. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER BYPASSED AND RECOVERED RECEIVE LINE CLOCK

AS RECEIVE TIMING SOURCE......................................................................................................................................... 280

FIGURE 82. WAVEFORMS OF THE SIGNALS CONNECTING THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL

EQUIPMENT WHEN THE SLIP BUFFER IS BYPASSED AND THE RECOVERED LINE CLOCK IS THE TIMING SOURCE OF THE RECEIVE

SECTION ..................................................................................................................................................................... 281

6.2.2.2 CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE SLIP

BUFFER IS ENABLED ............................................................................................................................................... 281

SLIP BUFFER STATUS REGISTER (SBSR) (INDIRECT ADDRESS = 0XNAH, 0X08H)...................................... 282

FIGURE 83. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER ENABLED OR ACTS AS FIFO..................... 283

FIGURE 84. WAVEFORMS OF THE SIGNALS THAT CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMI-

NAL EQUIPMENT WHEN THE SLIP BUFFER IS ENABLED................................................................................................... 284

6.2.2.3 CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE SLIP

BUFFER IS CONFIGURED AS FIFO ........................................................................................................................... 284

FIFO LATENCY REGISTER (FIFOL) (INDIRECT ADDRESS = 0XN0H, 0X17H) .............................................. 284

FIGURE 85. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER ENABLED OR ACTS AS FIFO..................... 285

FIGURE 86. WAVEFORMS OF THE SIGNALS THAT CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMI-

NAL EQUIPMENT WHEN THE SLIP BUFFER IS ACTED AS FIFO......................................................................................... 286

6.2.3 HIGH SPEED RECEIVE BACK-PLANE INTERFACE................................................................................................ 286

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ........................ 286

RECEIVE MULTIPLEX ENABLE BIT = 0 ........................................................................................................ 287

RECEIVE MULTIPLEX ENABLE BIT = 1 ........................................................................................................ 288

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H) ......................... 288

6.2.3.1 E1 RECEIVE INPUT INTERFACE - MVIP 2.048 MHZ ............................................................................................. 288

FIGURE 87. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING MVIP 2.048MBIT/S DATA BUS.................................. 289

FIGURE 88. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT MVIP 2.048MBIT/S ...................................... 289

6.2.3.2 E1 RECEIVE INPUT INTERFACE - 4.096 MHZ ....................................................................................................... 290

FIGURE 89. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 4.096MBIT/S DATA BUS ........................................... 290

FIGURE 90. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 4.096MBIT/S MODE ....................................... 291

6.2.3.3 E1 RECEIVE INPUT INTERFACE - 8.192 MHZ ....................................................................................................... 291

FIGURE 91. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 8.192MBIT/S DATA BUS ........................................... 292

FIGURE 92. TIMING DIAGRAM OF INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 8.192MBIT/S MODE........................................ 292

6.2.3.4 E1 RECEIVE INPUT INTERFACE - BIT-MULTIPLEXED 16.384MBIT/S....................................................................... 292

FIRST OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 293

SECOND OCTET OF 16.384MBIT/S DATA STREAM...................................................................................... 293

FIFTH OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 294

SIXTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 294

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................... 294

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 294

FIGURE 93. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384 MBIT/S DATA BUS ........................................ 295

FIGURE 94. TIMING SIGNAL WHEN THE FRAMER IS RUNNING AT BIT-MULTIPLEXED 16.384MBIT/S MODE .......................................... 295

6.2.3.5 E1 RECEIVE INPUT INTERFACE - HMVIP 16.384MBIT/S....................................................................................... 295

FIRST OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 296

VII

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