XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.1

FIGURE 38. TIMING DIAGRAM OF THE INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT BIT-MULTIPLEXED 16.384MBIT/S MODE 205

4.1.3.6 T1 TRANSMIT INPUT INTERFACE - HMVIP 16.384MBIT/S..................................................................................... 205

FIRST OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 206

NINTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 206

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................... 207

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................ 207

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................... 207

TENTH OCTET OF 16.384MBIT/S DATA STREAM......................................................................................... 207

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM..................................................................................... 207

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM............................................................................... 207

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 208

FIGURE 39. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT USING HMVIP 16.384MBIT/S DATA BUS .................... 209

FIGURE 40. TIMING DIAGRAM OF THE INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT HMVIP 16.384MBIT/S MODE ................ 209

4.1.3.7 T1 TRANSMIT INPUT INTERFACE - H.100 16.384MBIT/S....................................................................................... 209

FIRST OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 210

NINTH OCTET OF 16.384MBIT/S DATA STREAM ......................................................................................... 210

ELEVENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................... 211

THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM ................................................................................ 211

FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................... 211

TENTH OCTET OF 16.384MBIT/S DATA STREAM......................................................................................... 211

TWELFTH OCTET OF 16.384MBIT/S DATA STREAM..................................................................................... 211

FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM............................................................................... 211

SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 212

FIGURE 41. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT USING H.100 16.384MBIT/S DATA BUS ...................... 213

FIGURE 42. TIMING DIAGRAM OF THE INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT H.100 16.384MBIT/S MODE .................. 213

5.0 THE DS1 RECEIVE SECTION ............................................................................................................. 214

5.1 THE DS1 RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ......................................................... 214

5.1.1 DESCRIPTION OF THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK............................................. 214

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H)......................... 214

5.1.2 THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK OPERATING AT 1.544MBIT/S MODE .............. 214

SLIP BUFFER CONTROL REGISTER (SBCR) (INDIRECT ADDRESS = 0XN0H, 0X16H) .................................. 215

SLIP BUFFER CONTROL REGISTER (SBCR) (INDIRECT ADDRESS = 0XN0H, 0X16H) .................................. 215

TABLE 42: THE RECEIVE SERIAL CLOCK AND RECEIVE SINGLE-FRAME SYNCHRONIZATION SIGNALS FOR DIFFERENT SLIP BUFFER SETTINGS

216

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H)......................... 217

TABLE 43: THE RXTSB[2:0] BITS WHEN THE RECEIVE FRACTIONAL T1 OUTPUT BIT IS SET TO DIFFERENT VALUES .......................... 218

5.1.2.1 CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE SLIP

BUFFER IS BYPASSED ............................................................................................................................................. 218

FIGURE 43. INTERFACING XRT84L38 LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER BYPASSED AND RECOVERED RECEIVE LINE CLOCK

AS RECEIVE TIMING SOURCE ....................................................................................................................................... 219

FIGURE 44. WAVEFORMS OF THE SIGNALS CONNECTING THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL

EQUIPMENT WHEN THE SLIP BUFFER IS BYPASSED AND THE RECOVERED LINE CLOCK IS THE TIMING SOURCE OF THE RECEIVE

SECTION ..................................................................................................................................................................... 220

5.1.2.2 CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE SLIP

BUFFER IS ENABLED ............................................................................................................................................... 220

SLIP BUFFER STATUS REGISTER (SBSR) (INDIRECT ADDRESS = 0XNAH, 0X08H) ..................................... 221

FIGURE 45. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER ENABLED OR ACTS AS FIFO ................ 222

FIGURE 46. WAVEFORMS OF THE SIGNALS THAT CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMI-

NAL EQUIPMENT WHEN THE SLIP BUFFER IS ENABLED................................................................................................... 223

5.1.2.3 CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE SLIP

BUFFER IS CONFIGURED AS FIFO ........................................................................................................................... 223

FIFO LATENCY REGISTER (FIFOLR) (INDIRECT ADDRESS = 0XN0H, 0X17H) ............................................ 223

FIGURE 47. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH SLIP BUFFER ENABLED OR ACTS AS FIFO ................ 224

FIGURE 48. WAVEFORMS OF THE SIGNALS THAT CONNECT THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK TO THE LOCAL TERMI-

NAL EQUIPMENT WHEN THE SLIP BUFFER IS ACTED AS FIFO......................................................................................... 225

5.1.3 HIGH SPEED RECEIVE BACK-PLANE INTERFACE................................................................................................ 225

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X22H)......................... 225

TABLE 44: RECEIVE MULTIPLEX ENABLE BIT AND RECEIVE INTERFACE MODE SELECT [1:0] BITS WITH THE RESULTING RECEIVE BACK-PLANE

INTERFACE DATA RATES ............................................................................................................................................... 226

RECEIVE MULTIPLEX ENABLE BIT = 0......................................................................................................... 226

RECEIVE MULTIPLEX ENABLE BIT = 1......................................................................................................... 227

IV

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