XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

REV. 1.0.1

TABLE OF CONTENTS

XRT84L38

OCTAL T1/E1/J1 FRAMER

GENERAL DESCRIPTION................................................................................................ 1

FIGURE 1. XRT84L38 8-CHANNEL DS1 (T1/E1/J1) FRAMER ............................................................................................................ 1

APPLICATIONS .............................................................................................................................................. 2

FEATURES .................................................................................................................................................... 2

ORDERING INFORMATION ................................................................................................................... 3

FIGURE 2. PIN OUT OF THE XRT84L38 TOP VIEW (SEE PIN LIST FOR NAMES AND FUNCTION) ............................................................ 4

TABLE OF CONTENTS ..................................................................................................... I

TABLE 1: LIST BY PIN NUMBER ......................................................................................................................................................... 5

PIN DESCRIPTIONS ......................................................................................................... 5

TRANSMIT SERIAL DATA INPUT...................................................................................................................... 5

OVERHEAD INTERFACE ............................................................................................................................... 14

RECEIVE SERIAL DATA OUTPUT .................................................................................................................. 16

RECEIVE DECODER LIU INTERFACE ............................................................................................................. 23

TRANSMIT ENCODER LIU INTERFACE ........................................................................................................... 23

TIMING ....................................................................................................................................................... 24

LIU CONTROL ............................................................................................................................................. 25

JTAG......................................................................................................................................................... 26

MICROPROCESSOR INTERFACE.................................................................................................................... 27

POWER SUPPLY PINS ................................................................................................................................. 30

GROUND PINS ............................................................................................................................................ 30

NO CONNECT PINS ..................................................................................................................................... 31

ELECTRICAL CHARACTERISTICS................................................................................................................... 32

ABSOLUTE MAXIMUMS ................................................................................................................................ 32

DC ELECTRICAL CHARACTERISTICS............................................................................................................. 32

TABLE 2: XRT84L38 POWER CONSUMPTION ................................................................................................................................. 32

1.0 MICROPROCESSOR INTERFACE BLOCK ......................................................................................... 33

TABLE 3: µC/µP SELECTION TABLE ................................................................................................................................................ 33

1.1 CHANNEL SELECTION WITHIN THE FRAMER .............................................................................................. 34

TABLE 4: CHANNEL SELECTION ...................................................................................................................................................... 34

FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK.................................................................... 35

1.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL .............................................................................. 35

TABLE 5: XRT84L38 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE INTEL AND MOTOROLA MODES

35

TABLE 6: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS ...................................................................................................... 36

TABLE 7: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ............................................................................................. 36

1.3 INTERFACING THE XRT84L38 TO THE LOCAL µC/µP VIA THE MICROPROCESSOR INTERFACE BLOCK 36

1.3.1 INTERFACING THE FRAMER TO THE MICROPROCESSOR OVER AN 8 BIT WIDE BI-DIRECTIONAL DATA BUS 37

1.3.2 DATA ACCESS MODES............................................................................................................................................... 37

1.3.2.1 PROGRAMMED I/O ................................................................................................................................................ 37

1.3.2.2 DATA ACCESS USING PROGRAMMED I/O ............................................................................................................... 37

FIGURE 4. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ OPERATION ................................................................... 38

FIGURE 5. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O WRITE OPERATION ................................................................. 39

FIGURE 6. MOTOROLA µP INTERFACE SIGNALS DURING A PROGRAMMED I/O READ OPERATION ....................................................... 40

FIGURE 7. MOTOROLA µP INTERFACE SIGNAL DURING PROGRAMMED I/O WRITE OPERATION........................................................... 41

1.3.2.3 BURST MODE I/O FOR DATA ACCESS ................................................................................................................... 41

FIGURE 8. INTEL µP INTERFACE SIGNALS, DURING THE INITIAL READ OPERATION OF A BURST CYCLE .............................................. 43

FIGURE 9. INTEL µP INTERFACE SIGNALS, DURING SUBSEQUENT READ OPERATIONS OF A BURST I/O CYCLE ................................... 44

FIGURE 10. INTEL µP INTERFACE SIGNALS, DURING THE INITIAL WRITE OPERATION OF A BURST CYCLE ........................................... 46

FIGURE 11. µP INTERFACE SIGNALS, DURING SUBSEQUENT WRITE OPERATIONS OF A BURST I/O CYCLE ......................................... 47

FIGURE 12. MOTOROLA µP INTERFACE SIGNALS DURING THE INITIAL READ OPERATION OF A BURST CYCLE .................................... 48

FIGURE 13. MOTOROLA µP INTERFACE SIGNALS, DURING SUBSEQUENT READ OPERATIONS OF A BURST I/O CYCLE ........................ 49

FIGURE 14. MOTOROLA µP INTERFACE SIGNALS, DURING THE INITIAL WRITE OPERATION OF A BURST CYCLE .................................. 51

FIGURE 15. MOTOROLA µP INTERFACE SIGNALS DURING SUBSEQUENT WRITE OPERATIONS OF A BURST I/O CYCLE ........................ 52

1.4 DMA READ/WRITE OPERATIONS................................................................................................................... 52

DMA-0 Write DMA Interface ..................................................................................................................................... 53

FIGURE 16. DMA MODE FOR THE XRT84L38 AND A MICROPROCESSOR......................................................................................... 53

1.5 MEMORY AND REGISTER MAP ...................................................................................................................... 53

1.5.1 MEMORY MAPPED I/O INDIRECT ADDRESSING...................................................................................................... 53

I

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