XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.1

TABLE 8: ADDRESS MAP ................................................................................................................................................................ 54

1.6 DESCRIPTION OF THE CONTROL REGISTERS ............................................................................................ 55

TABLE 9: PMON T1/E1 RECEIVE LINE CODE (BIPOLAR) VIOLATION COUNTER ............................................................................... 159

TABLE 10: PMON T1/E1 RECEIVE LINE CODE (BIPOLAR) VIOLATION COUNTER ............................................................................. 159

TABLE 11: PMON T1/E1 RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER ............................................................................ 159

TABLE 12: PMON T1/E1 RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER ............................................................................ 159

TABLE 13: PMON T1/E1 RECEIVE SEVERELY ERRORED FRAME COUNTER ................................................................................... 160

TABLE 14: PMON T1/E1 RECEIVE CRC-4 BLOCK ERROR COUNTER - MSB ................................................................................. 160

TABLE 15: PMON T1/E1 RECEIVE CRC-4 BLOCK ERROR COUNTER - LSB .................................................................................. 160

TABLE 16: PMON T1/E1 RECEIVE FAR-END BLOCK ERROR COUNTER - MSB .............................................................................. 160

TABLE 17: PMON T1/E1 RECEIVE FAR END BLOCK ERROR COUNTER ......................................................................................... 161

TABLE 18: PMON T1/E1 RECEIVE SLIP COUNTER ....................................................................................................................... 161

TABLE 19: PMON T1/E1 RECEIVE LOSS OF FRAME COUNTER ..................................................................................................... 161

TABLE 20: PMON T1/E1 RECEIVE CHANGE OF FRAME ALIGNMENT COUNTER .............................................................................. 162

TABLE 21: PMON LAPD T1/E1 FRAME CHECK SEQUENCE ERROR COUNTER .............................................................................. 162

TABLE 22: T1/E1 PRBS BIT ERROR COUNTER MSB .................................................................................................................... 162

TABLE 23: T1/E1 PRBS BIT ERROR COUNTER LSB ..................................................................................................................... 163

TABLE 24: T1/E1 TRANSMIT SLIP COUNTER ................................................................................................................................. 163

1.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER ............................................................................... 164

TABLE 25: LIST OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS, IN EACH FRAMER ............................................. 164

TABLE 26: ADDRESS OF THE BLOCK INTERRUPT STATUS REGISTERS ............................................................................................ 165

TABLE 27: BLOCK INTERRUPT STATUS REGISTER ......................................................................................................................... 166

TABLE 28: BLOCK INTERRUPT ENABLE REGISTER ......................................................................................................................... 167

1.7.1 CONFIGURING THE INTERRUPT SYSTEM, AT THE FRAMER LEVEL .................................................................. 167

1.7.1.1 ENABLING/DISABLING THE FRAMER FOR INTERRUPT GENERATION ....................................................................... 167

TABLE 29: INTERRUPT CONTROL REGISTER .................................................................................................................................. 168

1.7.1.2 CONFIGURING THE INTERRUPT STATUS BITS WITHIN A GIVEN FRAMER TO BE RESET-UPON-READ OR WRITE-TO-CLEAR.

168

1.7.1.3 AUTOMATIC RESET OF INTERRUPT ENABLE BITS ................................................................................................. 168

2.0 THE E1 FRAMING STRUCTURE......................................................................................................... 170

2.1 THE SINGLE E1 FRAME ................................................................................................................................. 170

FIGURE 17. SINGLE E1 FRAME DIAGRAM...................................................................................................................................... 170

Timeslot 0 ............................................................................................................................................................... 170

Timeslot 0 octets within FAS frames ...................................................................................................................... 170

TABLE 30: BIT FORMAT OF TIMESLOT 0 OCTET WITHIN A FAS E1 FRAME ...................................................................................... 170

Bit 0—Si (International Bit) ..................................................................................................................................... 171

TABLE 31: BIT FORMAT OF TIMESLOT 0 OCTET WITHIN A NON-FAS E1 FRAME .............................................................................. 171

Bit 0—Si (International Bit) ..................................................................................................................................... 171

Bit 1—Fixed at “1”................................................................................................................................................... 171

Bit 2—A (FAS Frame Yellow Alarm Bit).................................................................................................................. 171

Bit 3 through 7—Sa4–Sa8 (National Bits) .............................................................................................................. 171

2.2 THE E1 MULTI-FRAME STRUCTURES.......................................................................................................... 171

2.2.1 THE CRC MULTI-FRAME STRUCTURE .................................................................................................................... 172

TABLE 32: BIT FORMAT OF ALL TIMESLOT 0 OCTETS WITHIN A CRC MULTI-FRAME ......................................................................... 172

2.2.2 CAS MULTI-FRAMES AND CHANNEL ASSOCIATED SIGNALING ........................................................................ 172

2.2.2.1 CHANNEL ASSOCIATED SIGNALING ..................................................................................................................... 173

FIGURE 18. FRAME/BYTE FORMAT OF THE CAS MULTI-FRAME STRUCTURE .................................................................................. 173

2.2.2.2 COMMON CHANNEL SIGNALING (CCS) ................................................................................................................ 174

FIGURE 19. E1 FRAME FORMAT ................................................................................................................................................... 174

3.0 THE DS1 FRAMING STRUCTURE ...................................................................................................... 175

FIGURE 20. T1 FRAME FORMAT ................................................................................................................................................... 175

3.1 T1 SUPER FRAME FORMAT (SF) .................................................................................................................. 175

FIGURE 21. T1 SUPERFRAME PCM FORMAT ................................................................................................................................ 176

TABLE 33: SUPERFRAME FORMAT ................................................................................................................................................ 176

3.2 T1 EXTENDED SUPERFRAME FORMAT ...................................................................................................... 177

FIGURE 22. T1 EXTENDED SUPERFRAME FORMAT ........................................................................................................................ 177

TABLE 34: EXTENDED SUPERFRAME FORMAT ............................................................................................................................... 177

3.3 SLC 96 FORMAT (SLC)................................................................................................................................... 179

TABLE 35: SLC®96 FS BIT CONTENTS ........................................................................................................................................ 179

4.0 THE DS1 TRANSMIT SECTION .......................................................................................................... 180

4.1 THE DS1 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK .......................................................... 180

4.1.1 DESCRIPTION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK .............................................. 180

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H) ........................ 180

4.1.2 BRIEF DISCUSSION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT 1.544MBIT/

II

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