XRT84L38 データシートの表示（PDF） - Exar Corporation
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XRT84L38 Datasheet PDF : 453 Pages
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XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
S MODE........................................................................................................................................................................ 181
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H)................................................. 181
TABLE 36: SIGNALS FOR DIFFERENT TRANSMIT TIMING SOURCES ................................................................................................... 182
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H)....................... 182
TABLE 37: THE TXTSB[3:0] BITS WHEN THE TRANSMIT FRACTIONAL T1 INPUT BIT IS SET TO DIFFERENT VALUES ............................ 183
4.1.2.1 CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF TRANSMIT
TIMING SOURCE = TXSERCLK_N ............................................................................................................................ 183
FIGURE 23. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH TXSERCLK_N AS TRANSMIT TIMING SOURCE ............ 184
FIGURE 24. WAVEFORMS OF THE SIGNALS THAT CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL
EQUIPMENT WITH THE TRANSMIT SERIAL CLOCK BEING THE TIMING SOURCE OF THE TRANSMIT SECTION ....................... 185
4.1.2.2 CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT IF THE TRANSMIT
TIMING SOURCE = OSCCLK .................................................................................................................................. 185
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H)................................................. 186
FIGURE 25. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT WITH THE OSCCLK DRIVEN DIVIDED CLOCK AS TRANSMIT TIM-
ING SOURCE................................................................................................................................................................ 187
FIGURE 26. WAVEFORMS OF THE SIGNALS CONNECTING THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL
EQUIPMENT WITH THE OSCCLK DRIVEN DIVIDED CLOCK AS THE TIMING SOURCE OF THE TRANSMIT SECTION ............... 188
4.1.2.3 CONNECT THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL EQUIPMENT FOR LOOP-TIM-
ING APPLICATIONS .................................................................................................................................................. 188
CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H).................................................. 189
FIGURE 27. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT WITH RECOVERED RECEIVE LINE CLOCK AS TRANSMIT TIMING
SOURCE...................................................................................................................................................................... 190
FIGURE 28. WAVEFORMS OF THE SIGNALS CONNECTING THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK TO THE LOCAL TERMINAL
EQUIPMENT WITH THE RECOVERED RECEIVE LINE CLOCK BEING THE TIMING SOURCE OF THE TRANSMIT SECTION ......... 191
4.1.3 BRIEF DISCUSSION OF THE TRANSMIT HIGH-SPEED BACK-PLANE INTERFACE ........................................... 191
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H)....................... 191
TABLE 38: TRANSMIT MULTIPLEX ENABLE BIT AND TRANSMIT INTERFACE MODE SELECT [1:0] BITS WITH THE RESULTING TRANSMIT BACK-
PLANE INTERFACE DATA RATES .................................................................................................................................... 192
TRANSMIT MULTIPLEX ENABLE BIT = 0 ...................................................................................................... 192
TRANSMIT MULTIPLEX ENABLE BIT = 1 ...................................................................................................... 193
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H)........................ 193
4.1.3.1 T1 TRANSMIT INPUT INTERFACE - MVIP 2.048 MHZ ........................................................................................... 194
TABLE 39: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ................................................................................................ 194
FIGURE 29. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT USING MVIP 2.048MBIT/S DATA BUS ......................... 195
FIGURE 30. TIMING DIAGRAM OF THE INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT MVIP 2.048MBIT/S MODE ..................... 195
4.1.3.2 T1 TRANSMIT INPUT INTERFACE - 4.096 MHZ ..................................................................................................... 195
TABLE 40: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ................................................................................................ 196
FIGURE 31. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT USING 4.096MBIT/S DATA BUS................................... 197
FIGURE 32. TIMING DIAGRAM OF THE INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 4.096MBIT/S MODE............................... 197
4.1.3.3 T1 TRANSMIT INPUT INTERFACE - 8.192 MHZ ..................................................................................................... 197
TABLE 41: THE MAPPING OF T1 FRAME INTO E1 FRAMING FORMAT ................................................................................................ 198
FIGURE 33. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT USING 8.192MBIT/S DATA BUS .................................. 199
FIGURE 34. TIMING DIAGRAM OF THE INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 8.192MBIT/S MODE............................... 199
4.1.3.4 T1 TRANSMIT INPUT INTERFACE - MULTIPLEXED 12.352MBIT/S ........................................................................... 199
FIRST OCTET OF 12.352MBIT/S DATA STREAM.......................................................................................... 200
SECOND OCTET OF 12.352MBIT/S DATA STREAM...................................................................................... 200
THIRD OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 200
SIXTH OCTET OF 12.352MBIT/S DATA STREAM ......................................................................................... 201
SEVENTH OCTET OF 12.352MBIT/S DATA STREAM .................................................................................... 201
EIGHTH OCTET OF 12.352MBIT/S DATA STREAM ....................................................................................... 201
NINETH OCTET OF 12.352MBIT/S DATA STREAM ....................................................................................... 201
FIGURE 35. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT USING BIT-MULTIPLEXED 12.352MBIT/S DATA BUS..... 202
FIGURE 36. TIMING DIAGRAM OF THE INPUT SIGNALS TO THE FRAMER WHEN RUNNING AT 12.352MBIT/S MODE............................. 202
4.1.3.5 T1 TRANSMIT INPUT INTERFACE - BIT-MULTIPLEXED 16.384MBIT/S..................................................................... 202
FIRST OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 203
NINETH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 203
TENTH OCTET OF 16.384MBIT/S DATA STREAM ........................................................................................ 203
THIRTEENTH OCTET OF 16.384MBIT/S DATA STREAM................................................................................ 204
FOURTEENTH OCTET OF 16.384MBIT/S DATA STREAM .............................................................................. 204
FIFTEENTH OCTET OF 16.384MBIT/S DATA STREAM .................................................................................. 204
SIXTEENTH OCTET OF 16.384MBIT/S DATA STREAM.................................................................................. 204
FIGURE 37. INTERFACING XRT84L38 TO THE LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ................................ 205
III
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