IDT82V2048 データシートの表示（PDF） - Integrated Device Technology
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IDT82V2048 Datasheet PDF : 61 Pages
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
SDO
/RDY
/ACK
Type
Pin No.
QFP144 BGA160
Description
O
83 K14 SDO: Serial Data Output
In serial host mode, the data is output on this pin. In serial write operation, SDO is always in High
impedance. In serial read operation, SDO is in High impedance only when SDI is in
address/command byte. Data on pin SDO is clocked out of the device on falling edges of SCLK if
pin CLKE is Low, or on rising edges of SCLK if pin CLKE is High.
RDY: Ready Output
In parallel Intel host mode, the high level of this pin reports to the host that bus cycle can be
completed, while low reports the host must insert wait states.
INT
O
82
Open
Drain
LP7/D7/AD7 I/O
28
LP6/D6/AD6
27
LP5/D5/AD5
26
LP4/D4/AD4 Tri-state 25
LP3/D3/AD3
24
LP2/D2/AD2
23
LP1/D1/AD1
22
LP0/D0/AD0
21
ACK: Acknowledge Output (Active Low)
In parallel Motorola host mode, the low level of this pin indicates that valid information on the data
bus is ready for a read operation or acknowledges the acceptance of the written data during a
write operation.
K13 INT: Interrupt (Active Low)
This is the open drain, active low interrupt output. Four sources may cause the interrupt (refer to
Interrupt Handling of Functional Description for details).
K1 LPn: Loopback Select 7~0
J1 In hardware control mode, pin LPn configures the corresponding channel in different loopback
J2 mode, as follows:
J3
J4
H2
H3
G2
LPn
Loopback Configuration
Low
Remote loopback.
VDDIO/2
No loopback.
High
Analog loopback.
Refer to Loopback Configuration of Functional Description for details.
Dn: Data Bus 7~0
In non-multiplexed host mode, these pins are the bi-directional data bus.
ADn: Address/Data Bus 7~0
In multiplexed host mode, these pins are the multiplexed bi-directional address/data bus.
In serial host mode, these pins should be grounded.
9
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