IDT82V2048 データシートの表示（PDF） - Integrated Device Technology

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IDT82V2048

OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

OCTAL T1/E1 SHORT HAUL

LINE INTERFACE UNIT

IDT82V2048

FEATURES

♦ Fully integrated octal T1/E1 short haul line interface which

supports 100Ω T1 twisted pair, 120Ω E1 twisted pair and 75Ω

E1 coaxial applications

♦ Selectable single rail or dual rail mode and AMI or HDB3/B8ZS

line encoder/decoder

♦ Built-in transmit pre-equalization meets G.703 & T1.102

♦ Selectable transmit/receive jitter attenuator meets ETSI CTR12/

13, ITU G.736, G.742,G.823 and AT&T Pub 62411 specifications

♦ SONET/SDH optimized jitter attenuator meets ITU G.783 map-

ping jitter specification

♦ Digital/analog LOS detector meets ITU G.775, ETS 300 233 and

T1.231

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ITU G.772 non-intrusive monitoring for in-service testing for

any one of channel1 to channel7

Low impedance transmit drivers with tri-state

Selectable hardware and parallel/serial host interface

Local, remote and inband loopback test functions

Hitless Protection Switching (HPS) for 1 to 1 protection with-

out relays

JTAG boundary scan for board test

3.3V supply with 5V tolerant I/O

Low power consumption

Operating Temperature Range: -40°C to +85°C

Available in 144-pin Thin Quad Flat Pack (TQFP_144_DA) and

160-pin Plastic Ball Grid Array (PBGA) packages

FUNCTIONAL BLOCK DIAGRAM

RTIPn

RRINGn

TTIPn

TRINGn

G.772

Monitor

Analog

Peak

Loopback Detector

Line

Driver

Clock

Generator

Slicer

LOS

Detector

CLK&Data

Recovery

(DPLL)

Digital

Loopback

Waveform

Shaper

Transmit

All Ones

One of Eight Identical Channels

Jitter

Attenuator

B8ZS/

HDB3/AMI

Decoder

Remote

Loopback

IBLC

Detector

AIS

Detector

Jitter

Attenuator

B8ZS/

HDB3/AMI

Encoder

IBLC

Generator

LOSn

RCLKn

RDn/RDPn

CVn/RDNn

TCLKn

TDn/TDPn

BPVIn/TDNn

Control Interface

Register

File

JTAG TAP

VDD IO

VDDT

VDDD

VDDA

Figure - 1. Block Diagram

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGES

1

© 2003 Integrated Device Technology, Inc.

DECEMBER 2003

DSC-6037/11

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