IDT82V2048 データシートの表示（PDF） - Integrated Device Technology

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IDT82V2048

OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

PIN DESCRIPTION (CONTINUED)

Name

TD0/TDP0

TD1/TDP1

TD2/TDP2

TD3/TDP3

TD4/TDP4

TD5/TDP5

TD6/TDP6

TD7/TDP7

BPVI0/TDN0

BPVI1/TDN1

BPVI2/TDN2

BPVI3/TDN3

BPVI4/TDN4

BPVI5/TDN5

BPVI6/TDN6

BPVI7/TDN7

Type

Pin No.

QFP144 BGA160

Description

37

N2 TDn: Transmit Data for Channel 0~7

30

L2 When the device is in Single Rail Mode, the NRZ data to be transmitted is input on this pin. Data on

80

L13 TDn is sampled into the device on falling edges of TCLKn, and encoded by AMI or HDB3/B8ZS line

73 N13 code rules before being transmitted to the line.

108 B13

101 D13 BPVIn: Bipolar Violation Insertion for Channel 0~7

8

D2 Bipolar violation insertion is available in Single Rail Mode 2 (see table-1) with AMI enabled. A low-to-

1

B2 high transition on this pin will make the next logic one to be transmitted on TDn the same polarity as the

I

previous pulse, and violate the AMI rule. This is for testing.

38

N3

31

L3 TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7

79

L12 When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input

72 N12 on this pin. Data on TDPn/TDNn are active high and sampled on falling edge of TCLKn. The line code in

109 B12 dual rail mode is as the follows :

102 D12

TDPn

TDNn

Output Pulse

7

D3

0

0

Space

144 B3

0

1

Negative Pulse

1

0

Positive Pulse

1

1

Space

TCLK0

TCLK1

TCLK2

TCLK3

TCLK4

TCLK5

TCLK6

TCLK7

Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding

channel into single rail mode 1 (see table-1 on Page14).

I

36

N1 TCLKn: Transmit Clock for Channel 0~7

29

L1 The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The

81

L14 transmit data at TDn/TDPn or TDNn is sampled into the device on falling edge of TCLKn.

74 N14 Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All

107 B14 One (TAO) state (when MCLK is clocked). In TAO state, the TAO generator adopts MCLK as the time

100 D14 reference.

9

D1 If TCLKn is Low, the corresponding transmit channel is set into power down state, while driver output

2

B1 ports become high impedance.

Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the

follows:

MCLK

TCLKn

Transmitter Mode

Clocked

Clocked

Normal operation

Clocked

High (≥ 16 MCLK) Transmit All One (TAO) signals to the line side in the

corresponding transmit channel.

Clocked Low (≥ 64 MCLK) Corresponding transmit channel is set into power down state.

High/Low TCLK1 is clocked TCLKn is clocked Normal operation

TCLKn is high Transmit All One (TAO) signals to the line side

(≥ 16 TCLK1) in the corresponding transmit channel.

TCLKn is low Corresponding transmit channel is set into

(≥ 64 TCLK1) power down state.

The receive path is not affected by the status of TCLK1. When

MCLK is high, all receive paths just slice the incoming data stream.

When MCLK is low, all the receive paths are powered down.

High/Low

TCLK1 is not All eight transmitters (TTIPn & TRINGn) will be in high impedance

available state.

(High/Low)

5

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