IDT82V2048 データシートの表示（PDF） - Integrated Device Technology
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IDT82V2048 Datasheet PDF : 61 Pages
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IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Name
Type
Pin No.
QFP144 BGA160
Description
RD0/RDP0 O
40
P2 RDn: Receive Data for Channel 0~7
RD1/RDP1
33
M2 In Single Rail Mode, the received NRZ data is output on this pin. The data is decoded by AMI or
RD2/RDP2 Tri-state 77
M13 HDB3/B8ZS line code rule.
RD3/RDP3
70
P13
RD4/RDP4
111 A13 CVn: Code Violation for Channel 0~7
RD5/RDP5
104 C13 In Single Rail Mode, the bipolar violation, code violation and excessive zeros will be reported by driving
RD6/RDP6
5
C2 pin CVn to high level for a full clock cycle. However, only bipolar violation is indicated when AMI
RD7/RDP7
142
A2 decoder is selected.
CV0/RDN0
41
CV1/RDN1
34
CV2/RDN2
76
CV3/RDN3
69
CV4/RDN4
112
CV5/RDN5
105
CV6/RDN6
4
CV7/RDN7
141
RCLK0
O
39
RCLK1
32
RCLK2 Tri-state 78
RCLK3
71
RCLK4
110
RCLK5
103
RCLK6
6
RCLK7
143
MCLK
I
10
LOS0
O
42
LOS1
35
LOS2
75
LOS3
68
LOS4
113
LOS5
106
LOS6
3
LOS7
140
P3 RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7
M3 In Dual Rail Mode with clock recovery, these pins output the NRZ data. A high signal on RDPn
M12 indicates the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the
P12 receipt of a negative pulse on RTIPn/RRINGn.
A12 The output data at RDn or RDPn/RDNn are valid on the falling edges of RCLK when the CLKE input is
C12 in High level, or valid on the rising edges of RCLK when CLKE is Low.
C3 In Dual Rail Mode without clock recovery, these pins output ht e raw RZ sliced data. In this data
A3 recovery mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is Low,
RDPn/RDNn is active low. When pin CLKE is High, RDPn/RDNn is active high.
In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will
either remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE
in register GCF (Global Configuration register).
RDn or RDPn/RDNn is set into high impedance when the corresponding receiver is power down.
P1 RCLKn: Receive Clock for Channel 0~7
M1 In clock recovery mode, this pin outputs the recovered clock from signal received on RTIPn/RRINGn.
M14 The received data are clocked out of the device on rising edges of RCLKn if pin CLKE is low, or on
P14 falling edges of RCLKn if pin CLKE is high.
A14 In data recovery mode, RCLKn is the output of an internal exclusive OR (XOR) which is connected with
C14 RDPn and RDNn. The clock is recovered from the signal on RCLKn externally.
C1 If receiver n is power down, the corresponding RCLKn is in high impedance.
A1
E1 MCLK: Master Clock
This is the independent, free running reference clock. A clock of 1.544 MHz (for T1 mode) or 2.048
MHz (for E1 mode) is supplied to this pin as the clock reference of the device for normal operation.
In receive path, when MCLK is high, the device slices the incoming bipolar line signal into RZ pulse
(Data Recovery mode). When MCLK is low, all the receivers are power down, and the output pins
RCLKn, RDPn and RDNn are switched to high impedance.
In transmit path, the operation mode is decided by the combination of MCLK and TCLKn (see TCLKn
pin description for detail).
Note that wait state generation via RDY/ACK is not available if MCLK is not provided.
K4 LOSn: Loss of Signal Output for Channel 0~7
K3 A high level on this pin indicates the loss of signal when there is no transition over a specified period of
K12 time and no enough ones density in the received signal. The transition will return to low automatically
K11 when there is enough transitions over a specified period of time with a certain ones density in the
E11 received signal. The LOS assertion and desertion criteria are described in the Functional Description.
E12
E3
E4
6
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