DS2148 データシートの表示（PDF） - Maxim Integrated

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DS2148

5V E1/T1/J1 Line Interface Unit

Maxim Integrated 

DS2148/DS21Q48

Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name,

DS2148T)

NAME

A0

to

A4

PIN

I/O

FUNCTION

11

Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1),

to

I serves as the address bus. In multiplexed bus operation (BIS1 = 0, BIS0 =

7

0), these pins are not used and should be tied low.

ALE(AS)

4

BIS0/BIS1 32/33

Address Latch Enable (Address Strobe). When using the parallel port

I

(BIS1 = 0) in multiplexed bus mode (BIS0 = 0), serves to demultiplex the

bus on a positive-going edge. In nonmultiplexed bus mode (BIS0 = 1),

should be tied low.

I

Bus Interface Select Bits 0 & 1. Used to select bus interface option. See

Table 2-1 for details.

Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz

BPCLK

31

O clock output that is referenced to RCLK selectable via CCR5.7 and

CCR5.6. In hardware mode, defaults to 16.384MHz output.

CS

1

I Active-Low Chip Select. Must be low to read or write to the device.

D0/AD0

19

Data Bus/Address/Data Bus. In non-multiplexed bus operation (BIS1 =

to

to

I/O 0, BIS0 = 1), serves as the data bus. In multiplexed bus operation (BIS1 =

D7/AD7

12

0, BIS0 = 0), serves as an 8-bit multiplexed address/data bus.

HRST

29

I

Active-Low Hardware Reset. Bringing HRST low will reset the DS2148

setting all control bits to their default state of all zeros.

Active-Low Interrupt. Flags host controller during conditions and

INT

23

O change of conditions defined in the Status Register. Active low, open

drain output.

Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is

applied at this pin. This clock is used internally for both clock/data

MCLK

30

I recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is

optional.

See Note 1 on clock accuracy at the end of this table.

NA

PBEO

-

I Not Assigned. Should be tied low.

PRBS Bit Error Output. The receiver will constantly search for a 215-1 or

a 220-1 PRBS depending on the ETS bit setting (CCR1.7). Remains high if

out of synchronization with the PRBS pattern. Goes low when

24

O synchronized to the PRBS pattern. Any errors in the received pattern after

synchronization will cause a positive going pulse (with same period as E1

or T1 clock) synchronous with RCLK. PRBS bit errors can also be

reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.

PBTS

Parallel Bus Type Select. When using the parallel port (BIS1 = 0), set

high to select Motorola bus timing, set low to select Intel bus timing. This

44

I

pin controls the function of the RD(DS), ALE(AS), and WR(R/W) pins. If

PBTS = 1 and BIS1 = 0, then these pins assume the Motorola function

listed in parenthesis (). In serial port mode, this pin should be tied low.

RCLK

40

O

Receive Clock. Buffered recovered clock from the line. Synchronous to

MCLK in absence of signal at RTIP and RRING.

Active-Low Read Input (Data Strobe). DS is active low when in

RD(DS)

2

I nonmultiplexed, Motorola mode. See the bus timing diagrams in Section

10.

RCL/LOTC

25

Receive Carrier Loss/Loss of Transmit Clock. An output which will

O

toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high

if the TCLK pin has not been toggled for 5µs ±2µs (CCR2.7 = 1). CCR2.7

defaults to logic 0 when in hardware mode.

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