ISP1562 データシートの表示（PDF） - NXP Semiconductors.
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ISP1562 Datasheet PDF : 94 Pages
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NXP Semiconductors
ISP1562
HS USB PCI host controller
Table 12. CC - Class Code register (address 09h) bit description
Bit
Symbol Description
23 to 16 BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller.
15 to 8 SCC[7:0] Sub-Class Code: 03h is the sub-class code assigned to this byte. It implies the USB host controller.
7 to 0
RLPI[7:0]
Register-Level Programming Interface: 10h is the programming interface code assigned to OHCI,
which is USB 1.1 specification compliant. 20h is the programming interface code assigned to EHCI,
which is USB 2.0 specification compliant.
8.2.1.7 CacheLine Size register
The CacheLine Size register is a read and write single-byte register that specifies the
system CacheLine size in units of DWORDs. This register must be implemented by
master devices that can generate the Memory Write and Invalidate command. The value
in this register is also used by master devices to determine whether to use Read, Read
Line or Read Multiple command to access the memory.
Slave devices that want to allow memory bursting using CacheLine-wrap addressing
mode must implement this register to know when a burst sequence wraps to the
beginning of the CacheLine.
This field must be initialized to logic 0 on activation of RST#. Table 13 shows the bit
description of the CacheLine Size register.
Table 13. CLS - CacheLine Size register (address 0Ch) bit description
Legend: * reset value
Bit
Symbol Access
Value Description
7 to 0 CLS[7:0] R/W
00h* CacheLine Size: This byte identifies the system CacheLine size.
8.2.1.8 Latency Timer register
This register specifies, in units of PCI bus clocks, the value of the Latency Timer for the
PCI bus master. Table 14 shows the bit description of the Latency Timer register.
Table 14. LT - Latency Timer register (address 0Dh) bit description
Legend: * reset value
Bit
Symbol Access Value Description
7 to 0 LT[7:0] R/W
00h*
Latency Timer: This byte identifies the latency timer.
8.2.1.9 Header Type register
The Header Type register identifies the layout of the second part of the predefined header,
beginning at byte 10h in configuration space. It also identifies whether the device contains
multiple functions. For bit allocation, see Table 15.
Table 15. HT - Header Type register (address 0Eh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
MFD
HT[6:0]
Reset
1
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
ISP1562_3
Product data sheet
Rev. 03 — 14 November 2008
© NXP B.V. 2008. All rights reserved.
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