ISP1562 データシートの表示（PDF） - NXP Semiconductors.

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ISP1562

Hi-Speed USB PCI host controller

NXP Semiconductors. 

NXP Semiconductors

ISP1562

HS USB PCI host controller

signal INTA#. These functions provide memory-mapped, addressable operational

registers as required in Open Host Controller Interface Specification for USB Rev. 1.0a

and Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.

Each function has its own configuration space. The PCI enumerator must allocate the

memory address space for each of these functions. Power management is implemented

in each PCI function and all power states are provided. This allows the system to achieve

low power consumption by switching off the functions that are not required.

8.1.1 PCI configuration space

PCI Local Bus Specification Rev. 2.2 requires that each of the three PCI functions of the

ISP1562 provides its own PCI configuration registers, which can vary in size. In addition to

the basic PCI configuration header registers, these functions implement capability

registers to support power management.

The registers of each of these functions are accessed by the respective driver. Section 8.2

provides a detailed description of various PCI configuration registers.

8.1.2 PCI initiator and target

A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI

transactions as a slave. In the ISP1562, two open host controllers and the enhanced host

controller function as both initiators or targets of PCI transactions issued by the host CPU.

All USB host controllers have their own operational registers that can be accessed by the

system driver software. Drivers use these registers to configure the host controller

hardware system, issue commands to it, and monitor the status of the current hardware

operation. The host controller plays the role of a PCI target. All operational registers of the

host controllers are the PCI transaction targets of the CPU.

Normal USB transfers require the host controller to access system memory fields, which

are allocated by USB HCDs and PCI drivers. The host controller hardware interacts with

the HCD by accessing these buffers. The host controller works as an initiator in this case

and becomes a PCI master.

8.2 PCI configuration registers

OHCI USB host controllers and the EHCI USB host controller contain two sets of

software-accessible hardware registers: PCI configuration registers and memory-mapped

host controller registers.

A set of configuration registers is implemented for each of the three PCI functions of the

ISP1562, see Table 3.

Remark: In addition to the normal PCI header, from offset index 00h to 3Fh,

implementation-specific registers are defined to support power management and

function-specific features.

ISP1562_3

Product data sheet

Rev. 03 — 14 November 2008

© NXP B.V. 2008. All rights reserved.

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