ISP1562 データシートの表示（PDF） - NXP Semiconductors.
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ISP1562 Datasheet PDF : 94 Pages
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NXP Semiconductors
ISP1562
HS USB PCI host controller
8.2.1.4 Status register
The Status register is a 2-byte read-only register used to record status information on PCI
bus-related events. For bit allocation, see Table 8.
Table 8. STATUS - Status register (address 06h) bit allocation
Bit
15
14
13
12
11
Symbol
DPE
SSE
RMA
RTA
STA
Reset
0
0
0
0
0
Access
R
R
R
R
R
Bit
7
6
5
4
3
Symbol
FBBC
reserved
66MC
CL
Reset
0
0
0
1
0
Access
R
R
R
R
R
10
9
DEVSELT[1:0]
0
1
R
R
2
1
reserved
0
0
R
R
8
MDPE
0
R
0
0
R
Table 9. STATUS - Status register (address 06h) bit description
Bit
Symbol Description
15
DPE
Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if
the parity error handling is disabled.
14
SSE
Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that
never assert SERR# do not need to implement this bit.
13
RMA
Received Master Abort: This bit must be set by a master device whenever its transaction, except for
special cycle, is terminated with master abort. All master devices must implement this bit.
12
RTA
Received Target Abort: This bit must be set by a master device whenever its transaction is
terminated with target abort. All master devices must implement this bit.
11
STA
Signaled Target Abort: This bit must be set by a target device whenever it terminates a transaction
with target abort. Devices that never signal target abort do not need to implement this bit.
10 to 9 DEVSELT DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three allowable timing to
[1:0]
assert DEVSEL#:
00b — Fast
01b — Medium
10b — Slow
11b — Reserved
These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any
bus command, except Configuration Read and Configuration Write.
8
MDPE
Master Data Parity Error: This bit is implemented by bus masters. It is set when the following three
conditions are met:
• The bus agent asserted PERR# itself, on a read; or observed PERR# asserted, on a write.
• The agent setting the bit acted as the bus master for the operation in which error occurred.
• PER (bit 6 in the Command register) is set.
7
FBBC
Fast Back-to-Back Capable: This read-only bit indicates whether the target is capable of accepting
fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to
logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise.
6
reserved -
ISP1562_3
Product data sheet
Rev. 03 — 14 November 2008
© NXP B.V. 2008. All rights reserved.
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