ISL6271AEVAL1 データシートの表示（PDF） - Intersil

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ISL6271AEVAL1

Setup Instructions for the ISL6271A Evaluation Kit

Intersil 

Setup Instructions for the ISL6271A Evaluation Kit

DVM Testing

Monitor Vcore DC voltage (TP8-TP9), while varying the voltage set-point using the I2C commands from the drop-

down voltage palate on the PC screen. The variable slew rate command-set can be verified by monitoring Vcore at

TP5 with a scope set on AC coupling and 200mV/Div sensitivity. The scope could be set to one-shot trigger off the

change in Vcore voltage, commanded by the user adjusting the trigger level about 50mV from the ‘0’V level in the

commanded direction. A more reliable, and repeatable, one-shot trigger is the incoming I2C clock signal. This signal

can be easily accessed on either end of the red conductor in the I2C interconnect cable. Now, when the ‘Write I2C’

command is given, the scope will trigger on the clock burst, and the Vcore voltage slew rate to the new voltage level

can be observed. This is illustrated below in Figure 13 for both a positive and negative slew command.

I2C Clock

(SCL)

Vcore

I2C data

(SDA)

LEGEND

Vcore

I2C Clock

I2C Data

FIGURE 13. VCORE SLEW RATE

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