VT82C596 データシートの表示（PDF） - Unspecified

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VT82C596

PCI INTEGRATED PERIPHERAL CONTROLLER

Unspecified 

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PCI Function 1 Registers – IDE Controller

Configuration Space IDE Header Registers

Offset PCI Configuration Space Header

1-0 Vendor ID

3-2 Device ID

5-4 Command

7-6 Status

8 Revision ID

9 Programming Interface

A Sub Class Code

B Base Class Code

C -reserved- (cache line size)

D Latency Timer

E Header Type

F Built In Self Test (BIST)

13-10 Base Address – Pri Data / Command

17-14 Base Address – Pri Control / Status

1B-18 Base Address – Sec Data / Command

1F-1C Base Address – Sec Control / Status

23-20 Base Address – Bus Master Control

24-2F -reserved- (unassigned)

30-33 -reserved- (expan ROM base addr)

34-3B -reserved- (unassigned)

3C Interrupt Line

3D Interrupt Pin

3E Minimum Grant

3F Maximum Latency

Default Acc

1106 RO

0571 RO

0080 RO

0280 RW

nn RO

85 RW

01 RO

01 RO

00 —

00 RW

00 RO

00 RO

000001F0 RO

000003F4 RO

00000170 RO

00000374 RO

0000CC01 RW

00 —

00 —

00 —

0E RW

00 RO

00 RO

00 RO

VT82C596B

Configuration Space IDE-Specific Registers

Offset Configuration Space IDE Registers Default Acc

40 Chip Enable

08 RW

41 IDE Configuration

02 RW

42 -reserved- (do not program)

09 RW

43 FIFO Configuration

3A RW

44 Miscellaneous Control 1

68 RW

45 Miscellaneous Control 2

00 RW

46 Miscellaneous Control 3

C0 RW

4B-48 Drive Timing Control

A8A8A8A8 RW

4C Address Setup Time

FF RW

4D -reserved- (do not program)

00 RW

4E Sec Non-1F0 Port Access Timing

FF RW

4F Pri Non-1F0 Port Access Timing

FF RW

53-50 UltraDMA33 Extd Timing Control 03030303 RW

54 UltraDMA FIFO Control

06 RW

55-5F -reserved-

00 —

61-60 IDE Primary Sector Size

0200 RW

62-67 -reserved-

00 —

69-68 IDE Secondary Sector Size

0200 RW

69-6F -reserved-

00 —

70 IDE Primary Status

00 RW

71 IDE Primary Interrupt Control

00 RW

72-73 -reserved-

00 —

74 IDE Primary Command 1

00 RW

75 IDE Primary Command 2

00 RW

76-77 -reserved-

00 —

78 IDE Secondary Status

00 RW

79 IDE Secondary Interrupt Control

00 RW

7A-7B -reserved-

00 —

7C IDE Secondary Command 1

00 RW

7D IDE Secondary Command 2

00 RW

7E-7F -reserved-

00 —

83-80 IDE Primary S/G Descriptor Address 0000 0000 RW

84-87 -reserved-

00 —

8B-88 IDE Secondary S/G Descriptor Addr 0000 0000 RW

8C-FF -reserved-

00 —

I/O Registers – IDE Controller (SFF 8038 v1.0 Compliant

Offset IDE I/O Registers

Default Acc

0 Primary Channel Command

00 RW

1 -reserved-

00 —

2 Primary Channel Status

00 WC

3 -reserved-

00 —

4-7 Primary Channel PRD Table Addr

00 RW

8 Secondary Channel Command

00 RW

9 -reserved-

00 —

A Secondary Channel Status

00 WC

B -reserved-

00 —

C-F Secondary Channel PRD Table Addr

00 RW

Revision 0.3 June 17, 1999

-24-

Register Overview

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