VT82C596 データシートの表示（PDF） - Unspecified

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VT82C596

PCI INTEGRATED PERIPHERAL CONTROLLER

Unspecified 

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VT82C596B

Signal Name

LID / GPI10

RI# / GPI12

THRM# / GPI8

SCIOUT# / GPO29

CPUSTP# / GPO17

PCISTP# / GPO18

ZZ / GPO19

SUSA#

SUSB# / GPO15

SUSC# / GPO16

SUSST1# / GPO20

SUSST2# / GPO21

Pin #

P16

P18

H19

F3

R1

R2

K16

W20

V19

U18

T17

T18

Power Management (continued)

I/O Signal Description

I Notebook Computer Display Lid Open / Closed Monitor. Used by the

Power Management subsystem to monitor the opening and closing of the

display lid of notebook computers. Can be used to detect either low-to-high

and/or high-to-low transitions to generate an SMI#. The VT82C596B

performs a 200 usec debounce of this input if Rx40[5] is set to 1. May

optionally be programmed as a general purpose input (Rx74[4]=1).

I Ring Indicator. May be connected to external modem circuitry to allow the

system to be re-activated by a received phone call. This input is referenced to

VCCSUS. May optionally be programmed as a general purpose input

(Rx74[6]=1).

I Thermal Detect. If the VT82C596B is enabled to allow it, asserting this

signal initiates hardware Clock Throttling mode. This causes STPCLK# to be

cycled at a preset programmable rate (see Function 3 configuration space

Rx4C). May optionally be programmed as a general purpose input

(Rx74[2]=1).

O ACPI System Control Interrupt. Connected to the external APIC if used.

May optionally be programmed as a general purpose output (Rx74[7]=0).

O CPU Clock Stop. Signals the system clock generator to disable the CPU clock

outputs. May optionally be programmed as a general purpose output

(Rx75[1]=1).

O PCI Clock Stop. Signals the system clock generator to disable the PCI clock

outputs. May optionally be programmed as a general purpose output

(Rx75[2]=1).

O L2 Cache SRAM Low Power Mode. Used to power down the L2 Cache

SRAMs during CPU Stop Clock state. May optionally be programmed as a

general purpose output (Rx75[3]=1).

O Suspend Plane A Control. Asserted during power management POS, STR,

and STD suspend states. Used to control the primary power plane.

O Suspend Plane B Control. Asserted during power management STR and STD

suspend states. Used to control the secondary power plane. May optionally be

programmed as a general purpose output (Rx75[0]=1).

O Suspend Plane C Control. Asserted during power management STD suspend

state. Used to control the tertiary power plane. May optionally be

programmed as a general purpose output (Rx75[0]=1).

O Suspend Status 1. Typically connected to the North Bridge (e.g., VT82C598

Apollo MVP3) to provide information on host clock status. Asserted when the

system may stop the host clock, such as Stop Clock or during POS, STR, or

STD suspend states. May optionally be programmed as a general purpose

output (Rx75[4]=1).

O Suspend Status 2. Typically connected to other system devices to provide

information on system suspend state. Asserted during POS, STR, or STD

suspend states. May optionally be programmed as a general purpose output

(Rx75[5]=1).

Revision 0.3 June 17, 1999

-19-

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