UPD72862 データシートの表示（PDF） - NEC => Renesas Technology

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UPD72862

IEEE1394 OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72862

2.1.5 Offset_08 Revision ID Register

This register specifies a revision number assigned by NEC Corporation for the µPD72862.

Bits

7-0

R/W

Description

R

Default value of 02H. It specifies the silicon revision. It will be incremented for subsequent

silicon revisions.

2.1.6 Offset_09 Class Code Register

This register identifies the class code, sub-class code, and programming interface of the µPD72862.

Bits

7-0

15-8

23-16

R/W

Description

R

Constant value of 10H. It specifies an IEEE1394 OpenHCI-compliant Host Controller.

R

Constant value of 00H. It specifies an “IEEE1394” type.

R

Constant value of 0CH. It specifies a “Serial Bus Controller”.

2.1.7 Offset_0C Cache Line Size Register

This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words.

The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0,

i.e. cache disabled.

Bits

7-0

R/W

R/W

Default value of 00H.

Description

2.1.8 Offset_0D Latency Timer Register

This register defines the maximum amount of time that the µPD72862 is permitted to retain ownership of the bus

after it has acquired bus ownership and initiated a subsequent transaction.

Bits

7-0

R/W

Description

R/W

Default value of 00H. It specifies the number of PCI-bus clocks that the µPD72862 may hold

the PCI bus as a bus-master.

2.1.9 Offset_0E Header Type Register

Bits

7-0

R/W

Description

R

Constant value of 00H. It specifies a single function device.

2.1.10 Offset_0F BIST Register

Bits

7-0

R/W

Description

R

Constant value of 00H. It specifies whether the device is capable of Built-in Self Test.

14

Data Sheet S14265EJ2V0DS00

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