EM78P569 データシートの表示（PDF） - ELAN Microelectronics
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EM78P569 Datasheet PDF : 58 Pages
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EM78P569
8-bit OTP Micro-controller
Bit 4 ~ Bit 5(AD8 ~ AD9) : The most significant 2 bit of 10-bit ADC conversion output data
Combine there two bits and RB PAGE1 as complete 10-bit ADC conversion output data.
Bit6 ~Bit7 : (undefined) not allowed to use
PAGE2 : (undefined) not allowed to use
PAGE3 (DT1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of PWM1)
7
6
5
4
3
2
1
0
-
-
-
-
-
- PWM1[9] PWM1[8]
R/W-0 R/W-0
Bit 0 ~ Bit 1 (PWM1[8] ~ PWM1[9]): The Most Significant Byte of PWM1 Duty Cycle
A specified value keeps the PWM1 output to stay at high until the value matches with TMR1.
Bit 2 ~ Bit 7 : (undefined) not allowed to use.
R8 (PORT8 I/O data, Data RAM address, PWM1 period)
PAGE0 (PORT8 I/O data register)
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (“VERSEL = 0” Data RAM address register)
7
6
5
4
3
2
1
0
RAM_A7 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 7 (RAM_A0 ~ RAM_A7) : data RAM address
The data RAM bank’s selection is from R7 PAGE1 bit0 ~ bit 1 (RAM_B0 ~ RAM_B1).
PAGE1 (“VERSEL = 1” Un-defined)
When “VERSEL = 1”, Data RAM address buffer is mapping to RB page2.
PAGE2 : (undefined) not allowed to use
PAGE3 (PRD1: Period of PWM1)
7
6
5
4
3
2
1
0
PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
The content of this register is a period (time base) of PWM1. The frequency of PWM1 is the reverse of the
period.
R9 (PORT9 I/O data, Data RAM data buffer, PWM2 duty)
PAGE0 (PORT9 I/O data register)
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register
User can use IOC register to define input or output each bit.
PAGE1 (Data RAM data register)
7
6
5
4
3
2
1
0
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
R/W
R/W
R/W
R/W R/W
R/W
R/W
R/W
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
17
8/19/2004 V4.4
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