EM78P569 データシートの表示（PDF） - ELAN Microelectronics
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EM78P569 Datasheet PDF : 58 Pages
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EM78P569
8-bit OTP Micro-controller
Bit 0 ~ Bit 7 (RAM_D0 ~ RAM_D7) : Data RAM’s data
The address for data RAM is accessed from R8 PAGE1. The data RAM bank is selected by R7 PAGE1 Bit
0 ~ Bit 1 (RAM_B0 ~ RAM_B1).
PAGE2 (Unused)
PAGE3 (DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of PWM2)
7
6
5
4
3
2
1
0
PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
A specified value keeps the output of PWM2 to stay at high until the value matches with TMR2.
RA (PLL, Main clock selection, Comparator flag, Watchdog timer, DAC input data buffer,
PWM2 duty, LCD option)
PAGE0 (PLL enable bit, Main clock selection bits, Comparator control bits, Watchdog timer enable bit)
7
6
5
4
3
2
1
0
0
PLLEN CLK2 CLK1 CLK0
-
- WDTEN
R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
R/W-0
Bit 0(WDTEN) : Watch dog control bit
0/1 disable/enable
User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If
the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616mS. If the
prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.
Bit 1 ~ Bit 2 : (undefined) not allowed to use
Bit 3 ~ Bit 5 (CLK0 ~ CLK2) : MAIN clock selection bits
User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.
PLLEN CLK2 CLK1 CLK0 Sub clock MAIN clock CPU clock
1
0
0
0
32.768kHz 447.829kHz 447.829kHz (Normal mode)
1
0
0
1
32.768kHz 895.658kHz 895.658kHz (Normal mode)
1
0
1
0
32.768kHz 1.791MHz 1.791MHz (Normal mode)
1
0
1
1
32.768kHz 3.582MHz 3.582MHz (Normal mode)
1
1
0
0
32.768kHz 7.165MHz 7.165MHz (Normal mode)
1
1
0
1
32.768kHz 10.747MHz 10.747MHz (Normal mode)
1
1
1
0
32.768kHz 14.331MHz 14.331MHz (Normal mode)
1
1
1
1
32.768kHz 17.91MHz 17.91MHz (Normal mode)
0 don’t care don’t care don’t care 32.768kHz don’t care 32.768kHz (Green mode)
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
0/1 disable PLL/enable PLL
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice.
18
8/19/2004 V4.4
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