EM78P569 データシートの表示（PDF） - ELAN Microelectronics

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EM78P569

8-BIT OTP MICRO-CONTROLLER

ELAN Microelectronics 

EM78P569

8-bit OTP Micro-controller

If PLL is enabled and main clock is selected to 3.5826MHz, the instruction clock is 0.895MHz/2

Fsco=0.895MHz/2

If PLL is disabled, the instruction clock is 32.768kHz/2 Fsco=32.768kHz/2.

Bit 3 (SCES) : SPI clock edge selection bit

1 Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level.

0 Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level.

Bit 4 (SE) : SPI shift enable bit

1 Start to shift, and keep on 1 while the current byte is still being transmitted.

0 Reset as soon as the shifting is complete, and the next byte is ready to shift.

<Note> This bit has to be reset in software.

Bit 5 (SRO) : SPI read overflow bit

1 A new data is received while the previous data is still being hold in the SPIB register. In this situation,

the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB

register even if the transmission is implemented only.

0 No overflow, <Note> This can only occur in slave mode.

Bit 6 (SPIE) : SPI enable bit

1 Enable SPI mode

0 Disable SPI mode

Bit 7 (RBF) : SPI read buffer full flag

1 Receive is finished, SPIB is full.

0 Receive is not finish yet, SPIB is empty.

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* This specification is subject to be changed without notice.

12

8/19/2004 V4.4

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