DS21448 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21448

3.3V E1/T1/J1 Quad Line Interface

Dallas Semiconductor -> Maxim Integrated 

DS21448 3.3V T1/E1/J1 Quad Line Interface

CCR2 (01H): Common Control Register 2

(MSB)

RLPIN

—

SCLD

CLDS

RHBE

THBE

TCES

(LSB)

RCES

NAME

RLPIN

—

SCLD

CLDS

RHBE

THBE

TCES

RCES

POSITION

CCR2.7

CCR2.6

CCR2.5

CCR2.4

CCR2.3

CCR2.2

CCR2.1

CCR2.0

FUNCTION

RCL/LOTC Pin Function Select. Forced to logic 0 in hardware mode.

0 = toggles high during a receive-carrier loss condition

1 = toggles high if TCLK does not transition for at least 5ms

Not Assigned. Should be set to 0 when written to.

Short Circuit-Limit Disable (ETS = 0). Controls the 50mA (RMS) current limiter.

0 = enable 50mA current limiter

1 = disable 50mA current limiter

Custom Line-Driver Select. Setting this bit to 1 redefines the operation of the transmit line

driver. When this bit is set to 1 and CCR4.5 = CCR4.6 = CCR4.7 = 0, the device generates a

square wave at the TTIP and TRING outputs instead of a normal waveform. When this bit is

set to 1 and CCR4.5 = CCR4.6 = CCR4.7 ¹ 0, the device forces TTIP and TRING outputs to

become open-drain drivers instead of their normal push-pull operation. This bit should be set

to 0 for normal operation of the device. Contact the factory for more details about how to use

this bit.

Receive HDB3/B8ZS Enable

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

Transmit HDB3/B8ZS Enable

0 = enable HDB3 (E1)/B8ZS (T1)

1 = disable HDB3 (E1)/B8ZS (T1)

Transmit Clock-Edge Select. Selects which TCLK edge to sample TPOS and TNEG.

0 = sample TPOS and TNEG on falling edge of TCLK

1 = sample TPOS and TNEG on rising edge of TCLK

Receive Clock-Edge Select. Selects which RCLK edge to update RPOS and RNEG.

0 = update RPOS and RNEG on rising edge of RCLK

1 = update RPOS and RNEG on falling edge of RCLK

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