DS21448 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21448

3.3V E1/T1/J1 Quad Line Interface

Dallas Semiconductor -> Maxim Integrated 

DS21448 3.3V T1/E1/J1 Quad Line Interface

Table 4-G. Parallel Port Mode Selection

PBTS

0

0

1

1

BIS0

0

1

0

1

PROCESSOR

Intel

Intel

Motorola

Motorola

BUS INTERFACE TYPE

Parallel Port Mode (Multiplexed)

Parallel Port Mode (Nonmultiplexed)

Parallel Port Mode (Multiplexed)

Parallel Port Mode (Nonmultiplexed)

4.3.2 Register Map

Table 4-H shows the typical register map for all four ports. Use the appropriate chip select (CS1, CS2, CS3, or CS4)

to access a channel’s register map.

Table 4-H. Register Map

NAME

R/W

ADDRESS

FUNCTION

CCR1

R/W

00h

Common Control Register 1

CCR2

R/W

01h

Common Control Register 2

CCR3

R/W

02h

Common Control Register 3

CCR4

R/W

03h

Common Control Register 4

CCR5

R/W

04h

Common Control Register 5

CCR6

R/W

05h

Common Control Register 6

SR

R

06h

Status Register

IMR

R/W

07h

Interrupt Mask Register

RIR1

R

08h

Receive Information Register 1

RIR2

R

09h

Receive Information Register 2

IBCC

R/W

0Ah

In-Band Code Control Register

TCD1

R/W

0Bh

Transmit Code Definition Register 1

TCD2

R/W

0Ch

Transmit Code Definition Register 2

RUPCD1

R/W

0Dh

Receive-Up Code Definition Register 1

RUPCD2

R/W

0Eh

Receive-Up Code Definition Register 2

RDNCD1

R/W

0Fh

Receive-Down Code Definition Register 1

RDNCD2

R/W

10h

Receive-Down Code Definition Register 2

ECR1

R

11h

Error Count Register 1

ECR2

R

12h

Error Count Register 2

TEST1

R/W

13h

Test 1

TEST2

R/W

14h

Test 2

TEST2

R/W

15h

Test 3

—

—

(Note 1) —

Note 1: Register addresses 16h–1Fh do not exist.

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