DS21448 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS21448 Datasheet PDF : 60 Pages
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DS21448 3.3V T1/E1/J1 Quad Line Interface
functions have been combined and affect all four channels in the device and/or treat the receive and transmit paths
as one block. Restrictions when using the hardware mode include the following:
· BPCLK pins only output a 16.384MHz signal.
· The RCL/LOTC pins are designated to RCL.
· The RHBE and THBE control bits are combined and controlled by HBE.
· RSCLKE and TSCLKE bits are combined and controlled by SCLKE.
· TCES and RCES are combined and controlled by CES.
· The transmitter functions are combined and controlled by TX1 and TX0.
· Loopback functions are controlled by LOOP1 and LOOP0.
· JABDS defaults to 128-bit buffer depth.
· All other control bits default to logic 0.
Table 4-A. Loopback Control in Hardware Mode
LOOPBACK
Remote Loopback
Local Loopback
Analog Loopback
No Loopback
SYMBOL
RLB
LLB
ALB
—
LOOP1
1
1
0
0
LOOP0
1
0
1
0
Table 4-B. Transmit Data Control in Hardware Mode
TRANSMIT DATA
SYMBOL
TX1
TX0
Unframed All Ones
TUA1
1
1
Alternating Ones and Zeros
TAOZ
1
0
PRBS
TPRBSE
0
1
TPOS and TNEG
—
0
0
Table 4-C. Receive Sensitivity Settings in Hardware Mode
EGL
0
1
1
0
ETS
0 (E1)
0 (E1)
1 (T1)
1 (T1)
RECEIVE SENSITIVITY (dB)
-12 (short haul)
-43 (long haul)
-30 (limited long haul)
-36 (long haul)
Table 4-D. Monitor Gain Settings in Hardware Mode
MM1
0
0
1
1
MM0
0
1
0
1
INTERNAL LINEAR GAIN BOOST (dB)
Normal operation (no boost)
20
26
32
Table 4-E. Internal Rx Termination Select in Hardware Mode
RT1
RT0
0
0
0
1
1
0
1
1
INTERNAL RECEIVE
TERMINATION CONFIGURATION
Internal receive-side termination disabled
Internal receive-side 120Ω enabled
Internal receive-side 100Ω enabled
Internal receive-side 75Ω enabled
Table 4-F. MCLK Selection in Hardware Mode
MCLK (MHz)
JAMUX
ETS
2.048
0
0
2.048
1
1
1.544
0
1
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