DS21448 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS21448 Datasheet PDF : 60 Pages
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DS21448 3.3V T1/E1/J1 Quad Line Interface
Figure 4-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2
ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK)
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SDI
0
A1
A2
A3
A4
A5
(LSB)
WRITE ACCESS ENABLED
SDO
0
B
DO
D1
D2
D3
(MSB) (LSB)
D4
D5
D6
D7
(MSB)
Figure 4-6. Serial Port Operation for Write Access (R = 0) Modes 3 and 4
ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK)
SCLK 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SDI
0
A1
A2
A3
A4
A5
(LSB)
WRITE ACCESS ENABLED
SDO
0
B
DO
D1
D2
D3
(MSB) (LSB)
D4
D5
D6
D7
(MSB)
4.3 Parallel Port Operation
The option for either multiplexed bus operation (BIS0 = 0) or nonmultiplexed bus operation (BIS0 = 1) is available
when using the parallel interface. The DS21448 can operate with either Intel or Motorola bus timing configurations.
If the PBTS pin is wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus
signals are listed in parentheses (). Four sets of identical register maps exist, one for each channel. See Table 4-H
for register names and addresses. Use the appropriate chip select (CS1, CS2, CS3, or CS4) to access a channel’s
register map. See the timing diagrams in Section 10 for more details. Hardware and serial port modes are not
supported when using parallel port operation.
4.3.1 Device Power-Up and Reset
The DS21448 resets itself upon power-up, setting all writeable registers to 00h and clearing the status and
information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the power
supplies have settled, initialize all control registers to the desired settings, then toggle the LIRST bit (CCR3.2). The
DS21448 can at any time be reset to the default settings by bringing HRST low (level triggered) or by powering
down and powering up again.
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