ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

一致するリスト

ADSP-2191MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

ADSP-2191

For current information contact Analog Devices at 800/262-5643

September 2001

The Host port is most efficient when using the DSP as a

slave and uses DMA to automate the incrementing of

addresses for these accesses. In this case, an address does

not have to be transferred from the Host for every

data transfer.

Host Port Acknowledge (HACK) Modes

The Host port supports a number of modes (or protocols)

for generating a HACK output for the host. The host selects

ACK or Ready Modes using the HACK_P and HACK pins.

The Host port also supports two modes for address control:

Address Latch Enable (ALE) and Address Cycle Control

(ACC) modes. The DSP auto-detects ALE versus ACC

Mode from the HALE and HWR inputs.

The host port HACK signal polarity is selected (only at

reset) as active high or active low, depending on the value

driven on the HACK_P pin.The HACK polarity is stored

into the host port configuration register as a read only bit.

The DSP uses HACK to indicate to the Host when to

complete an access. For a read transaction, a Host can

proceed and complete an access when valid data is present

in the read buffer and the host port is not busy doing a write.

For a write transactions, a Host can complete an access

when the write buffer is not full and the host port is not busy

doing a write.

Two mode bits in the Host Port configuration register

HPCR [7:6] define the functionality of the HACK line.

HPCR6 is initialized at reset based on the values driven on

HACK and HACK_P pins (shown in Table 5); HPCR7 is

always cleared (0) at reset. HPCR [7:6] can be modified

after reset by a write access to the host port

configuration register.

Table 5. Host Port Acknowledge Mode Selection

Values Driven At

Reset

HACK_P HACK

0

0

0

1

1

0

1

1

HPCR [7:6]

Initial Values

Bit 7

0

0

0

0

Bit 6

1

0

0

1

Acknowledge

Mode

Ready Mode

ACK Mode

ACK Mode

Ready Mode

The functional modes selected by HPCR [7:6] are as follows

(assuming active high signal):

• ACK Mode—Acknowledge is active on strobes; HACK

goes high from the leading edge of the strobe to indicate

when the access can complete. After the Host samples the

HACK active, it can complete the access by removing the

strobe.The host port then removes the HACK.

• Ready Mode—Ready active on strobes, goes low to insert

wait state during the access.If the host port can not

complete the access, it de-asserts the HACK/READY

line. In this case, the Host has to extend the access by

keeping the strobe asserted. When the Host samples the

HACK asserted, it can then proceed and complete the

access by de-asserting the strobe.

While in Address Cycle Control (ACC) mode and the ACK

or Ready acknowledge modes, the HACK is returned active

for any address cycle.

Host Port Chip Selects

There are two chip-select signals associated with the Host

Port: HCMS and HCIOMS. The Host Chip Memory

Select (HCMS) lets the Host select the DSP and directly

access the DSP’s internal/external memory space or boot

memory space. The Host Chip I/O Memory Select

(HCIOMS) lets the Host select the DSP and directly access

the DSP’s internal I/O memory space.

Before starting a direct access, the Host configures Host

port interface registers, specifying the width of external data

bus (8- or 16-bit) and the target address page (in the IJPG

register). The DSP generates the needed memory select

signals during the access, based on the target address. The

Host port interface combines the data from one, two, or

three consecutive Host accesses (up to one 24-bit value) into

a single DMA bus access to prefetch Host direct reads or to

post direct writes. During assembly of larger words, the Host

port interface asserts ACK for each byte access that does

not start a read or complete a write. Otherwise, the Host

port interface asserts ACK when it has completed the

memory access successfully.

DSP Serial Ports (SPORTs)

The ADSP-2191 incorporates three complete synchronous

serial ports (SPORT0, SPORT1, and SPORT2) for serial

and multiprocessor communications. The SPORTs

support the following features:

• Bidirectional operation—each SPORT has independent

transmit and receive pins.

• Buffered (8-deep) transmit and receive ports—each port

has a data register for transferring data words to and from

other DSP components and shift registers for shifting data

in and out of the data registers.

• Clocking—each transmit and receive port can either use

an external serial clock (≤75 MHz) or generate its own,

in frequencies ranging from 1144 Hz to 75 MHz.

10

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrC

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

Share Link: