ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices

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ADSP-2191MKCA-160X

DSP Microcomputer

Analog Devices 

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ADSP-2191

For current information contact Analog Devices at 800/262-5643

September 2001

a peripheral to one of the 12 user-defined interrupts. These

assignments determine the priority of each peripheral for

interrupt service.

There are three serial ports on the ADSP-2191 that provide

a complete synchronous, full-duplex serial interface. This

interface includes optional companding in hardware and a

wide variety of framed or frameless data transmit and receive

modes of operation. Each serial port can transmit or receive

an internal or external, programmable serial clock and

frame syncs. Each serial port supports 128-channel Time

Division Multiplexing.

The ADSP-2191 provides up to sixteen general-purpose

I/O pins, which are programmable as either inputs or

outputs. Eight of these pins are dedicated general purpose

Programmable Flag pins. The other eight of them are mul-

tifunctional pins, acting as general purpose I/O pins when

the DSP connects to an 8-bit external data bus and acting

as the upper eight data pins when the DSP connects to a

16-bit external data bus. These Programmable Flag pins can

implement edge- or level-sensitive interrupts, some of which

can be used to base the execution of conditional

instructions.

Three programmable interval timers generate periodic

interrupts. Each timer can be independently set to operate

in one of three modes:

• Pulse Waveform Generation mode

• Pulsewidth Count/Capture mode

• External Event Watchdog mode

Each timer has one bi-directional pin and four registers that

implement its mode of operation: A 7-bit configuration

register, a 32-bit count register, a 32-bit period register, and

a 32-bit pulsewidth register. A single status register supports

all three timers. A bit in the mode status register globally

enables or disables all three timers, and a bit in each timer’s

configuration register enables or disables the corresponding

timer independently of the others.

Memory Architecture

The ADSP-2191 DSP provides 64K words of on-chip

SRAM memory. This memory is divided into two 32K

blocks located on memory Page 0 in the DSP’s memory

map. In addition to the internal and external memory space,

the ADSP-2191 can address two additional and separate

off-chip memory spaces: I/O space and boot space.

As shown in Figure 2, the DSP’s two internal memory

blocks populate all of Page 0. The entire DSP memory map

consists of 256 pages (Pages 0−255), and each page is 64K

words long. External memory space consists of four

memory banks (banks 0–3) and supports a wide variety of

SRAM memory devices. Each bank is selectable using the

memory select pins (MS3–0) and has configurable page

boundaries, waitstates, and waitstate modes. The 1K word

of on-chip boot-ROM populates the top of Page 255 while

the remaining 254 pages are addressable off-chip. I/O

memory pages differ from external memory pages in that

I/O pages are 1K word long, and the external I/O pages have

their own select pin (IOMS). Pages 0–31 of I/O memory

space reside on-chip and contain the configuration registers

for the peripherals. Both the ADSP-2191 and DMA-capa-

ble peripherals can access the DSP’s entire memory map.

Internal (On-Chip) Memory

The ADSP-2191’s unified program and data memory space

consists of 16M locations that are accessible through two

24-bit address buses, the PMA and DMA buses. The DSP

uses slightly different mechanisms to generate a 24-bit

address for each bus. The DSP has three functions that

support access to the full memory map.

• The DAGs generate 24-bit addresses for data fetches from

the entire DSP memory address range. Because DAG

index (address) registers are 16 bits wide and hold the

lower 16 bits of the address, each of the DAGs has its own

8-bit page register (DMPGx) to hold the most significant

eight address bits. Before a DAG generates an address,

the program must set the DAG’s DMPGx register to the

appropriate memory page.

• The Program Sequencer generates the addresses for

instruction fetches. For relative addressing instructions,

the program sequencer bases addresses for relative jumps,

calls, and loops on the 24-bit Program Counter (PC). In

direct addressing instructions (two-word instructions),

the instruction provides an immediate 24-bit address

value. The PC allows linear addressing of the full 24-bit

address range.

• For indirect jumps and calls that use a 16-bit DAG

address register for part of the branch address, the

Program Sequencer relies on an 8-bit Indirect Jump page

(IJPG) register to supply the most significant eight

address bits. Before a cross page jump or call, the program

must set the program sequencer’s IJPG register to the

appropriate memory page.

The ADSP-2191 has 1K word of on-chip ROM that holds

boot routines. If peripheral booting is selected, the DSP

starts executing instructions from the on-chip boot ROM,

which starts the boot process from the selected peripheral.

For more information, see Booting Modes on page 14. The

on-chip boot ROM is located on Page 255 in the DSP’s

memory space map.

External (Off-Chip) Memory

Each of the ADSP-2191’s off-chip memory spaces has a

separate control register, so applications can configure

unique access parameters for each space. The access param-

eters include read and write wait counts, waitstate

completion mode, I/O clock divide ratio, write hold time

extension, strobe polarity, and data bus width. The core

6

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrC

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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