ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

一致するリスト

ADSP-2191MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

ADSP-2191

For current information contact Analog Devices at 800/262-5643

September 2001

Interrupts

The interrupt controller lets the DSP respond to 17 inter-

rupts with minimum overhead. The controller implements

an interrupt priority scheme as shown in Table 1. Applica-

tions can use the unassigned slots for software and

peripheral interrupts.

Table 1. Interrupt Priorities/Addresses

priority level of 11 are aliased to the lowest priority bit

position (15) in these registers and share vector address

0x00 01E0.

Table 2. Peripheral Interrupts and Priority at Reset

Interrupt

Reset

ID Priority

Interrupt

Emulator (NMI)—

Highest Priority

Reset (NMI)

Power-Down (NMI)

Loop and PC Stack

Emulation Kernel

User Assigned Interrupt

User Assigned Interrupt

User Assigned Interrupt

User Assigned Interrupt

User Assigned Interrupt

User Assigned Interrupt

User Assigned Interrupt

User Assigned Interrupt

IMASK/ Vector

IRPTL Address1

NA

NA

0

0x00 0000

1

0x00 0020

2

0x00 0040

3

0x00 0060

4

0x00 0080

5

0x00 00A0

6

0x00 00C0

7

0x00 00E0

8

0x00 0100

9

0x00 0120

10

0x00 0140

11

0x00 0160

Slave DMA/Host Port Interface

SPORT0 Receive

SPORT0 Transmit

SPORT1 Receive

SPORT1 Transmit

SPORT2 Receive/SPI0

SPORT2 Transmit/SPI1

UART Receive

UART Transmit

Timer A

Timer B

Timer C

Programmable Flag 0 (any PFx)

Programmable Flag 1 (any PFx)

Memory DMA port

00

11

22

33

44

55

66

77

88

99

10 10

11 11

12 11

13 11

14 11

User Assigned Interrupt

12

0x00 0180

User Assigned Interrupt

13

0x00 01A0

User Assigned Interrupt

14

0x00 01C0

User Assigned Interrupt— 15

Lowest Priority

0x00 01E0

1These interrupt vectors start at address 0x10000 when the DSP is in

“no-boot”, run-form-external memory mode.

Table 2 shows the ID and priority at reset of each of the

peripheral interrupts. To assign the peripheral interrupts a

different priority, applications write the new priority to their

corresponding control bits (determined by their ID) in the

Interrupt Priority Control register. The peripheral inter-

rupt’s position in the IMASK and IRPTL register and its

vector address depend on its priority level, as shown in

Table 1. Because the IMASK and IRPTL registers are

limited to 16 bits, any peripheral interrupts assigned a

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially.

Interrupts can be masked or unmasked with the IMASK

register. Individual interrupt requests are logically ANDed

with the bits in IMASK; the highest priority unmasked

interrupt is then selected. The emulation, power-down, and

reset interrupts are nonmaskable with the IMASK register,

but software can use the DIS INT instruction to mask the

power-down interrupt.

The Interrupt Control (ICNTL) register controls interrupt

nesting and enables or disables interrupts globally. The gen-

eral-purpose Programmable Flag (PFx) pins can be

configured as outputs, can implement software interrupts,

and (as inputs) can implement hardware interrupts. Pro-

8

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrC

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

Share Link: