ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

一致するリスト

ADSP-2191MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

September 2001 For current information contact Analog Devices at 800/262-5643

ADSP-2191

grammable Flag pin interrupts can be configured for

level-sensitive, single edge-sensitive, or dual edge-

sensitive operation.

Table 3. Interrupt Control (ICNTL) Register Bits

Bit

0–3

4

5

6

7

8–9

10

11

12–15

Description

Reserved

Interrupt Nesting Enable

Global Interrupt Enable

Reserved

MAC-Biased Rounding Enable

Reserved

PC Stack Interrupt Enable

Loop Stack Interrupt Enable

Reserved

The IRPTL register is used to force and clear interrupts.

On-chip stacks preserve the processor status and are auto-

matically maintained during interrupt handling. To support

interrupt, loop, and subroutine nesting, the PC stack is

33 levels deep, the loop stack is eight levels deep, and the

status stack is 16 levels deep. To prevent stack overflow, the

PC stack can generate a stack-level interrupt if the PC stack

falls below three locations full or rises above 28

locations full.

The following instructions globally enable or disable

interrupt servicing, regardless of the state of IMASK.

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG

and computational registers exist. Switching between the

primary and secondary registers lets programs quickly

service interrupts, while preserving the DSP’s state.

DMA Controller

The ADSP-2191 has a DMA controller that supports

automated data transfers with minimal overhead for the

DSP core. Cycle stealing DMA transfers can occur between

the ADSP-2191’s internal memory and any of its

DMA-capable peripherals. Additionally, DMA transfers

can be accomplished between any of the DMA-capable

peripherals and external devices connected to the external

memory interface. DMA-capable peripherals include the

Host port, SPORTs, SPI ports, and UART. Each individual

DMA-capable peripheral has a dedicated DMA channel. To

describe each DMA sequence, the DMA controller uses a

set of parameters—called a DMA descriptor. When succes-

sive DMA sequences are needed, these DMA descriptors

can be linked or chained together, so the completion of one

DMA sequence auto-initiates and starts the next sequence.

DMA sequences do not contend for bus access with the DSP

core, instead DMAs “steal” cycles to access memory.

All DMA transfers use the DMA bus shown in the func-

tional block diagram on page 1. Because all of the

peripherals use the same bus, arbitration for DMA bus

access is needed. The arbitration for DMA bus access

appears in Table 4.

Table 4. I/O Bus Arbitration Priority

DMA Bus Master

Arbitration Priority

SPORT0 Receive DMA

0—Highest

SPORT1 Receive DMA

1

SPORT2 Receive DMA

2

SPORT0 Transmit DMA

3

SPORT1 Transmit DMA

4

SPORT2 Transmit DMA

5

SPI0 Receive/Transmit DMA 6

SPI1 Receive/Transmit DMA 7

UART Receive DMA

8

UART Transmit DMA

9

Host Port DMA

10

Memory DMA

11—Lowest

Host Port

The ADSP-2191’s Host port functions as a slave on the

external bus of an external Host. The Host port interface

lets a Host read from or write to the DSP’s memory space,

boot space, or internal I/O space. Examples of Hosts include

external microcontrollers, microprocessors, or ASICs.

The Host port is a multiplexed address and data bus that

provides both an 8-bit and a 16-bit data path and operates

using an asynchronous transmission protocol. Through this

port, an off-chip Host can directly access the DSP’s entire

memory space map, boot memory space, and internal I/O

space. To access the DSP’s internal memory space, a Host

steals one cycle per access from the DSP. A Host access to

the DSP’s external memory uses the external port interface

and does not stall (or steal cycles from) the DSP’s core.

Because a Host can access internal I/O memory space, a

Host can control any of the DSP’s I/O mapped peripherals.

REV. PrC

This information applies to a product under development. Its characteristics and specifications are subject to change with-

9

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

Share Link: