ISP1562 データシートの表示（PDF） - NXP Semiconductors.

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ISP1562

Hi-Speed USB PCI host controller

NXP Semiconductors. 

NXP Semiconductors

ISP1562

HS USB PCI host controller

Table 40. PCI bus power and clock control …continued

Originating device’s Secondary bus Resultant actions by bridge (either direct or

bridge PM state

PM state

indirect)

D2

B2

clock stopped on secondary bus

D3hot

B2, B3

clock stopped and PCI VCC removed from secondary

bus (B3 only); for definition of B2_B3#, see Table 39

D3cold

B3

none

8.2.3.6 Data register

The Data register is an optional, 1-byte register that provides a mechanism for the

function to report state dependent operating data, such as power consumed or heat

dissipated. Table 41 shows the bit description of the register.

Table 41. DATA - Data register bit description

Address: Value read from address 34h + 7h

Legend: * reset value

Bit

Symbol Access Value Description

7 to 0 DATA[7:0] R

00h*

DATA: This register is used to report the state dependent data requested by the

D_S field of the PMCSR register. The value of this register is scaled by the value

reported by the DS field of the PMCSR register.

ISP1562_3

Product data sheet

Rev. 03 — 14 November 2008

© NXP B.V. 2008. All rights reserved.

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