ISP1562 データシートの表示（PDF） - NXP Semiconductors.

部品番号

コンポーネント説明

一致するリスト

ISP1562

Hi-Speed USB PCI host controller

NXP Semiconductors. 

NXP Semiconductors

ISP1562

HS USB PCI host controller

8.2.2 Enhanced host controller-specific PCI registers

In addition to the PCI configuration header registers, EHCI needs some additional PCI

configuration space registers to indicate the serial bus release number, downstream port

wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF).

The EHCI-specific PCI registers are given in Table 25.

Table 25. EHCI-specific PCI registers

Offset

Register

60h

Serial Bus Release Number (SBRN)

61h

Frame Length Adjustment (FLADJ)

62h to 63h

Port Wake Capability (PORTWAKECAP)

8.2.2.1 SBRN register

The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit

description is given in Table 26. This register contains the release number of the USB

specification with which this USB host controller module is compliant.

Table 26. SBRN - Serial Bus Release Number register (address 60h) bit description

Legend: * reset value

Bit

Symbol Access Value Description

7 to 0 SBRN[7:0] R

20h*

Serial Bus Specification Release Number: This register value is to identify

Universal Serial Bus Specification Rev. 2.0. All other combinations are reserved.

8.2.2.2 FLADJ register

This feature is used to adjust any offset from the clock source that generates the clock that

drives the SOF counter. When a new value is written to these six bits, the length of the

frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is

given in Table 27.

Table 27. FLADJ - Frame Length Adjustment register (address 61h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved[1]

FLADJ[5:0]

Reset

0

0

1

0

0

0

0

0

Access

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

[1] The reserved bits should always be written with the reset value.

Table 28. FLADJ - Frame Length Adjustment register (address 61h) bit description

Bit

Symbol

Description

7 to 6 reserved

-

5 to 0

FLADJ[5:0]

Frame Length Timing Value: Each decimal value change to this register corresponds to 16

high-speed bit times. The SOF cycle time, number of SOF counter clock periods to generate a

SOF microframe length, is equal to 59488 + value in this field. The default value is decimal 32

(20h), which gives a SOF cycle time of 60000; see Table 29.

ISP1562_3

Product data sheet

Rev. 03 — 14 November 2008

© NXP B.V. 2008. All rights reserved.

23 of 93

Share Link: