ISP1562 データシートの表示（PDF） - NXP Semiconductors.

部品番号

コンポーネント説明

一致するリスト

ISP1562

Hi-Speed USB PCI host controller

NXP Semiconductors. 

NXP Semiconductors

ISP1562

HS USB PCI host controller

Table 29. FLADJ value as a function of SOF cycle time

FLADJ value

SOF cycle time (480 MHz)

0 (00h)

59488

1 (01h)

59504

2 (02h)

59520

:

:

31 (1Fh)

59984

32 (20h)

60000

:

:

62 (3Eh)

60480

63 (3Fh)

60496

8.2.2.3 PORTWAKECAP register

Port Wake Capability (PORTWAKECAP) is a 2-byte register used to establish a policy

about which ports are for wake events; see Table 30. Bit positions 15 to 1 in the mask

correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit

position indicates that a device connected below the port can be enabled as a wake-up

device and the port may be enabled for disconnect or connect, or overcurrent events as

wake-up events. This is an information only mask register. The bits in this register do not

affect the actual operation of the EHCI host controller. The system-specific policy can be

established by BIOS initializing this register to a system-specific value. The system

software uses the information in this register when enabling devices and ports for remote

wake-up.

Table 30. PORTWAKECAP - Port Wake Capability register (address 62h) bit description

Legend: * reset value

Bit Symbol

Access Value

Description

15 to 0 PORTWAKE R/W

CAP[15:0]

0007h* Port Wake-Up Capability Mask: EHCI does not implement this feature.

8.2.3 Power management registers

Table 31. Power management registers

Offset

Register

Value read from address 34h + 0h

Capability Identifier (CAP_ID)

Value read from address 34h + 1h

Next Item Pointer (NEXT_ITEM_PTR)

Value read from address 34h + 2h

Power Management Capabilities (PMC)

Value read from address 34h + 4h

Power Management Control/Status (PMCSR)

Value read from address 34h + 6h

Power Management Control/Status PCI-to-PCI Bridge

Support Extensions (PMCSR_BSE)

Value read from address 34h + 7h

Data

8.2.3.1 CAP_ID register

The Capability Identifier (CAP_ID) register when read by the system software as 01h

indicates that the data structure currently being pointed to is the PCI power management

data structure. Each function of a PCI device may have only one item in its capability list

with CAP_ID set to 01h. The bit description of the register is given in Table 32.

ISP1562_3

Product data sheet

Rev. 03 — 14 November 2008

© NXP B.V. 2008. All rights reserved.

24 of 93

Share Link: