XRT83VL38 データシートの表示（PDF） - Unspecified
部品番号
コンポーネント説明
一致するリスト
XRT83VL38 Datasheet PDF : 95 Pages
| |||
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
SIGNAL NAME
RDY_DTACK
EQC4
µPTS1
µPTS2
LEAD # TYPE
DESCRIPTION
A6
O Ready Output (Data Transfer Acknowledge Output) - Host mode
Intel bus timing: RDY is asserted “High” to indicate the device has completed a
read or write operation.
Motorola bus timing: DTACK is asserted “Low” to indicate the device has com-
pleted a read or write cycle.
A6
I Equalizer Control Input pin 4 - Hardware mode
Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and
Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND
TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 31.
NOTE: Internally pulled “Low” with a 50k resistor.
Microprocessor Type Select Input Pins - Host Mode:
J16
I Microprocessor Type Select Input Bit 1
L15
Microprocessor Type Select Input Bit 2
PTS2
0
0
1
1
PTS1
0
1
0
1
P Type
Intel 8051 Asynchronous
Motorola Asynchronous
Power PC Synchronous
MPC8xx Motorola Synchronous
RCLKE
TCLKE
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]/SDO
LOOP1_4
LOOP0_4
LOOP1_5
LOOP0_5
LOOP1_6
LOOP0_6
LOOP1_7
LOOP0_7
J16
Receive Clock Edge - Hardware mode
SEE”RECEIVE CLOCK EDGE - HARDWARE MODE” ON PAGE 7.
Transmit Clock Edge - Hardware mode
L15
SEE”TRANSMIT CLOCK EDGE - HARDWARE MODE” ON PAGE 7.
NOTE: These pins are internally pulled “Low” with a 50k resistor.
Microprocessor Read/Write Data Bus Pins - Host mode
T7
I/O Data Bus[7]
U7
Data Bus[6]
V7
Data Bus[5]
V8
Data Bus[4]
V9
Data Bus[3]
U8
Data Bus[2]
U9
Data Bus[1]
R7
Data Bus[0] if SER_PAR = 0
or Serial Data Input if SER_PAR = 1
Loop-back Control Pins, Bits [1:0] Channel_[7:4] - Hardware Mode
T7
Pins 67-74 and 173-180 control which Loop-Back mode is selected per channel.
U7
SEE”LOOP-BACK CONTROL PINS, BITS [1:0] CHANNEL_[7:0]” ON
V7
PAGE 17.
V8
NOTE: Internally pulled “Low” with a 50k resistor for all channels.
V9
U8
U9
R7
12
Share Link: 