XRT83VL38 データシートの表示（PDF） - Unspecified
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XRT83VL38 Datasheet PDF : 95 Pages
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REV. 1.0.1
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME LEAD # TYPE
DESCRIPTION
Loop-back Control Pins, Bits [1:0] Channel_[7:0]
LOOP1_0
A10
I Loop-back Control bit 1, Channel _0
LOOP0_0
C10
Loop-back Control bit 0, Channel _0
LOOP1_1
A11
Loop-back Control bit 1, Channel _1
LOOP0_1
B10
Loop-back Control bit 0, Channel _1
LOOP1_2
C11
Loop-back Control bit 1, Channel _2
LOOP0_2
D11
Loop-back Control bit 0, Channel _2
LOOP1_3
A12
Loop-back Control bit 1, Channel _3
LOOP0_3
B11
Loop-back Control bit 0, Channel _3
LOOP1_4
T7
Loop-back Control bit 1, Channel _4
LOOP0_4
U7
Loop-back Control bit 0, Channel _4
LOOP1_5
V7
Loop-back Control bit 1, Channel _5
LOOP0_5
V8
Loop-back Control bit 0, Channel _5
LOOP1_6
V9
Loop-back Control bit 1, Channel _6
LOOP0_6
U8
Loop-back Control bit 0, Channel _6
LOOP1_7
U9
Loop-back Control bit 1, Channel _7
LOOP0_7
R7
Loop-back Control bit 0, Channel _7
In Hardware mode, these pins control the Loop-Back mode for each channel_n per
the following table.
LOOP1_n LOOP0_n
MODE
0
0
Normal Mode No Loop-Back Channel_n
0
1
Local Loop-Back Channel_n
1
0
Remote Loop-Back Channel_n
1
1
Digital Loop-Back Channel_n
A[1]
A10
A[0]/SDI
C10
A[3]
A11
A[2]
B10
A[5]
C11
A[4]
D11
A[7]
A12
A[6]
B11
D[7]
T7
D[6]
U7
D[5]
V7
D[4]
V8
D[3]
V9
D[2]
U8
D[1]
U9
D[0]/SDO
R7
Microprocessor Address A[7:0] and Data Bus Pins D[7:0] - Host mode
These pins are microprocessor address and data bus pins. SEE”MICROPROCES-
SOR INTERFACE ADDRESS BUS PINS - HOST MODE:” ON PAGE 13. and
see “Microprocessor Read/Write Data Bus Pins - Host mode” on
page 12.
NOTE: These pins are internally pulled “Low” with a 50kresistor.
17
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