XRT83VL38 データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

一致するリスト

XRT83VL38

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Unspecified 

REV. 1.0.1

XRT83VL38

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

SIGNAL NAME LEAD # TYPE

DESCRIPTION

TNEG_0

C4

CODES_0

C4

TNEG_1

B5

CODES_1

TNEG_2

D13

CODES_2

TNEG_3

B15

CODES_3

TNEG_4

U4

CODES_4

TNEG_5

V5

CODES_5

TNEG_6

U14

CODES_6

TNEG_7

R14

CODES_7

I Transmitter Negative NRZ Data Input for Channel _0

Dual-Rail mode

This signal is the negative-rail input data for transmitter 0.

Single-Rail mode

This pin can be left unconnected.

Coding Select for Channel _0 - Hardware mode and Single-Rail mode

Connecting this pin “Low” enables HDB3 in E1 or B8ZS in T1 encoding and decoding

for Channel _0. Connecting this pin “High” selects AMI data format.

Transmitter Negative NRZ Data Input for Channel _1

Coding Select for Channel _1

Transmitter Negative NRZ Data Input for Channel _2

Coding Select for Channel _2

Transmitter Negative NRZ Data Input for Channel _3

Coding Select for Channel _3

Transmitter Negative NRZ Data Input for Channel _4

Coding Select for Channel _4

Transmitter Negative NRZ Data Input for Channel _5

Coding Select for Channel _5

Transmitter Negative NRZ Data Input for Channel _6

Coding Select for Channel _6

Transmitter Negative NRZ Data Input for Channel _7

Coding Select for Channel _7

NOTE: Internally pulled “Low” with a 50k resistor for each channel.

TCLK_0

B4

TCLK_1

A3

TCLK_2

A15

TCLK_3

C14

TCLK_4

T3

TCLK_5

T5

TCLK_6

V16

TCLK_7

U15

I Transmitter Clock Input for Channel _0 - Host mode and Hardware mode

E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm.

During normal operation TCLK_0 is used for sampling input data at TPOS_0/

TDATA_0 and TNEG_0/CODES_0 while MCLK is used as the timing reference for the

transmit pulse shaping circuit.

Transmitter Clock Input for Channel _1

Transmitter Clock Input for Channel _2

Transmitter Clock Input for Channel _3

Transmitter Clock Input for Channel _4

Transmitter Clock Input for Channel _5

Transmitter Clock Input for Channel _6

Transmitter Clock Input for Channel _7

NOTE: Internally pulled “Low” with a 50k resistor for all channels.

9

Share Link: