XRT83VL38 データシートの表示（PDF） - Unspecified

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XRT83VL38

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Unspecified 

XRT83VL38

REV. 1.0.1

OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

MICROPROCESSOR INTERFACE

SIGNAL NAME

HW_HOST

WR_R/W

EQC0

RD_DS

EQC1

ALE_AS

EQC2

CS

EQC3

LEAD # TYPE

DESCRIPTION

T10

I Mode Control Input

This pin selects Hardware or Host mode. Leave this pin unconnected or tie “High”

to select Hardware mode.

For Host mode, this pin must be tied “Low”.

NOTE: Internally pulled “High” with a 50k resistor.

D7

I Write Input (Read/Write) - Host mode:

Intel bus timing: A “Low” pulse on WR selects a write operation when CS pin is

“Low”.

Motorola bus timing: A “High” pulse on R/W selects a read operation and a “Low”

pulse on R/W selects a write operation when CS is “Low”.

D7

Equalizer Control Input pin 0 - Hardware mode

Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and

Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND

TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 31.

NOTE: Internally pulled “Low” with a 50k resistor.

C7

I Read Input (Data Strobe) - Host mode

Intel bus timing: A “Low” pulse on RD selects a read operation when the CS pin is

“Low”.

Motorola bus timing: A “Low” pulse on DS indicates a read or write operation when

the CS pin is “Low”.

C7

Equalizer Control Input pin 1 - Hardware mode

Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and

Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND

TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 31.

NOTE: Internally pulled “Low” with a 50k resistor.

A7

I Address Latch Input (Address Strobe) - Host mode

Intel bus timing: The address inputs are latched into the internal register on the fall-

ing edge of ALE.

Motorola bus timing: The address inputs are latched into the internal register on

the falling edge of AS.

A7

Equalizer Control Input pin 2 - Hardware mode

Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and

Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND

TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 31.

NOTE: Internally pulled “Low” with a 50k resistor.

B7

I Chip Select Input - Host mode:

This signal must be “Low” in order to access the parallel port.

B7

Equalizer Control Input pin 3 - Hardware mode:

Pins EQC0, EQC1, EQC2, EQC3 and EQC4 select the Receive Equalizer and

Transmitter Line Build Out. SEE”RECEIVE EQUALIZER CONTROL AND

TRANSMIT LINE BUILD-OUT SETTINGS” ON PAGE 31.

NOTE: Internally pulled “Low” with a 50k resistor.

11

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