XRT83VL38 データシートの表示（PDF） - Unspecified
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XRT83VL38 Datasheet PDF : 95 Pages
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REV. 1.0.1
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL
NAME
CLKSEL0
CLKSEL1
CLKSEL2
LEAD # TYPE
DESCRIPTION
A8
I Clock Select inputs for Master Clock Synthesizer - Hardware mode
B8
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be
C8
used to generate a master clock from an external accurate clock source according to
the table below.
In Hardware mode, the MCLKRATE control signal is generated from the state of
EQC[4:0] inputs.
In Host mode, the state of these pins are ignored and the master frequency PLL is con-
trolled by the corresponding interface bits. See Table 40 register address 10000001
MCLKE1
kHz
2048
2048
2048
1544
1544
2048
MCLKT1
kHz
2048
2048
1544
1544
1544
1544
CLKSEL 2 CLKSEL1 CLKSEL0 MCLKRATE
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
CLKOUT
kHz
2048
1544
2048
1544
2048
1544
NOTE: These pins are internally pulled “Low” with a 50k resistor.
15
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