ZR36067 データシートの表示（PDF） - Unspecified

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ZR36067

AV PCI CONTROLLER

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AV PCI CONTROLLER

and “Gib” Endian formats are supported where applicable (Refer

to the PCI Multimedia Design Guide, Revision 1.0).

4.2.2 Display Modes

The display mode can be configured to either emulated inter-

laced video (both input fields are displayed simultaneously on

the non-interlaced monitor) or single field display. The latter is

appropriate for motion artifact elimination when displaying live or

decompressed Motion JPEG video.

4.2.3 Frame Grabbing

The ZR36067 can grab video frames (scaled or non scaled), or

fields, in any of the pixel formats listed above, directly into

system memory, eliminating the need for memory on the add-in

board.

4.2.4 Overlay Control

Graphics overlay is supported, in that display memory areas that

are “owned” by graphics applications, may not be loaded with

video pixels, allowing true windowing and overlay. The software

driver prepares a masking map of the video rectangle, and the

ZR36067 uses this map for masking decision, when transferring

the pixels to the display memory.

4.3 Host Control/Communication Services

4.3.1 Application-Specific Registers (ASRs)

The name “application-specific” distinguishes these registers

from the PCI configuration space registers. These memory

mapped registers provide the host software with full control over

the operation of the ZR36067. The ZR36067 claims a contigu-

ous space of 4 KBytes in system memory.

4.3.2 GuestBus

Host software control over non-PCI devices, such as a Motion

JPEG codec, an MPEG decoder, a video encoder, etc., is done

through the ZR36067’s GuestBus. Host accesses to these

“guest” devices, mapped as application specific registers inside

the ZR36067, are output as GuestBus cycles. Such accesses

can either use the PostOffice handshaking protocol, or the Code

DMA Controller. The first method is adequate for commands,

configuration data, etc., while the second method provides a

faster channel, and is intended for continuous transfer of data

such as a compressed bitstream.

4.3.3 PostOffice Handshaking Protocol

The ZR36067 PostOffice handshaking protocol, implemented

over the GuestBus, allows host accesses to relatively slow guest

devices, with no degradation of the PCI bus performance.

4.3.4 Still Transfer Mechanism

The ZR36067 supports a dedicated Still Transfer port, by means

of which the host writes (reads) image pixels in JPEG Still Image

Compression (Decompression) mode. The Still Transfer port is

mapped inside the ASR area, and a special controller intercon-

nects this port to the ZR36067’s extended video bus (24 bits

RGB). The Still Transfer handshake protocol enables high rate

pixels transfer between the system memory and the JPEG pro-

cessor via the ZR36067.

4.3.5 I2C Port

A software-driven I2C port allows controlling of I2C devices.

4.3.6 Interrupt Manager

Interrupt requests associated with several internal and external

conditions are sent to the host via the PCI bus (using INTA).

Selection of interrupt originators is programmable.

4.4 Code DMA Controller

The ZR36067 includes a DMA channel for transferring data

between the system memory and a selected device on the Code

Bus or GuestBus. Two configurations are supported:

• MPEG mode. The data flow is unidirectional, from the sys-

tem memory, to the ZR36067’s GuestBus.

• JPEG mode. The data flow is bidirectional, and the direction

is determined by the selected sub-mode. In JPEG Compres-

sion, the data flows from the Codec bus to the system

memory. In JPEG Decompression, the data flows from the

system memory to the Codec bus.

4.4.1 MPEG Mode

In MPEG mode, the data flows from the system memory to the

ZR36067’s GuestBus. Typically, this would be a compressed bit-

stream, to be decompressed by a device such as an MPEG

decoder attached to the GuestBus. Other examples are sampled

audio (WAV data), MIDI token stream, etc. Temporary latencies

on the PCI bus or the GuestBus are handled without loss of data.

The GuestBus master simultaneously serves the PostOffice

accesses and the code DMA transfers: DMA transfers are

viewed as the “main” task of the GuestBus master, while any

number of PostOffice requests may occasionally interrupt the

DMA traffic.

The DMA controller supports both auto-initialized (cyclic) block

transfers, or single block transfers. The size of the destination

block in main memory can be selected out of several possible

sizes, ranging from 8 KBytes up to 256 KBytes. The destination

block may also be virtually split into several sub-blocks, allowing

the ZR36067 to interrupt the host when a sub-block has been

transferred. This feature provides the software with a means of

optimizing the refill accesses according to the application

requirements and the disk performance.

4.4.2 JPEG Modes

In the JPEG modes, the data flows between the system memory

and the ZR36067’s Codec bus. In JPEG Compression, from the

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