UPD72874 データシートの表示（PDF） - NEC => Renesas Technology

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UPD72874

IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER

NEC => Renesas Technology 

µPD72874

3.2 CardBus Mode Configuration Register (CARD_ON = High)

31

24 23

16 15

08 07

00

Device ID

Vendor ID

00H

Status

Command

04H

Class Code

Revision ID

08H

BIST

Header Type

Latency Timer

Cache Line Size

0CH

Base Address 0

10H

Base Address 1 (Cardbus Status Reg) Note

14H

Base Address 2 (Cardbus Status Reg) Note

18H

Reserved

1CH

Reserved

20H

Reserved

24H

Cardbus CIS Pointer Note

28H

Subsystem ID

Subsystem Vendor ID

2CH

Reserved

30H

Reserved

Cap_Ptr

34H

Reserved

38H

Max_Lat

Min_Gnt

Interrupt Pin

Interrupt Line

3CH

PCI_OHCI_Control

40H

Reserved

44H

Reserved

48H

Reserved

4CH

Reserved

50H

Reserved

54H

Reserved

58H

Reserved

5CH

Power Management Capabilities

Next_Item_Ptr

Cap_ID

60H

Reserved

Power Management Control/Status

64H

Reserved

68H

Reserved

6CH

Reserved

70H

Reserved

74H

Reserved

78H

Reserved

7CH

CIS Area Note

80H

FCH

Note Different from PCI Bus Mode Configuration Register.

26

Preliminary Data Sheet S15306EJ2V0DS

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