UPD72874 データシートの表示（PDF） - NEC => Renesas Technology
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UPD72874 Datasheet PDF : 40 Pages
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µPD72874
3.1.21 Offset_62 Power Management Capabilities Register
This is a 16-bit read-only register that provides information on the power management capabilities of the
µPD72874.
Bits
2-0
3
4
5
8-6
9
10
15-11
R/W
Description
R
Version Constant value of 010. The power management registers are implemented as
defined in revision 1.1 of PCI Bus Power Management Interface Specification.
R
PME clock Constant value of 0.
R
Reserved Constant value of 0.
R
DSI Constant value of 0.
R
Auxiliary Power Default value of 000. This field reports the Vaux power requirements for the
µPD72874. This data is programable from EEPROM.
111 – 375 mA maximum current required for a 3.3 Vaux,
110 – 320 mA maximum current required for a 3.3 Vaux,
101 – 270 mA maximum current required for a 3.3 Vaux,
100 – 220 mA maximum current required for a 3.3 Vaux,
011 – 160 mA maximum current required for a 3.3 Vaux,
010 – 100 mA maximum current required for a 3.3 Vaux,
001 – 55 mA maximum current required for a 3.3 Vaux,
000 – 0 (self powered)
R
D1_support Constant value of 1. The µPD72874 supports the D1 Power Management state.
R
D2_support Constant value of 1. The µPD72874 supports the D2 Power Management state.
R
PME_support
D3SUP = ‘High’ : Constant value of 11111.
D3SUP = ‘Low’ : Constant value of 01111.
This field indicates the power states in which the µPD72874 may assert PME. A value of “0” for
any bit indicates that the function is not capable of asserting the PME signal while in that power
state.
bit (11) – PME_D0. PME can be asserted from D0.
bit (12) – PME_D1. PME can be asserted from D1.
bit (13) – PME_D2. PME can be asserted from D2.
bit (14) – PME_D3hot. PME can be asserted from D3hot.
bit (15) – PME_D3cold. PME can be asserted from D3cold.
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Preliminary Data Sheet S15306EJ2V0DS
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