UPD72874 データシートの表示（PDF） - NEC => Renesas Technology

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UPD72874

IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER

NEC => Renesas Technology 

µPD72874

2.2 Port Status Page (Page 000)

1000

1001

1010

1011

1100

1101

1110

1111

Figure 2-2. Port Status Page

0

1

AStat

Negotiated_speed

2

3

4

BStat

Child

Int_enable

Fault

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

5

Connected

6

Bias

Reserved

7

Disabled

Field

AStat

BStat

Child

Connected

Bias

Disabled

Negotiated_

Speed

Int_enable

Fault

Reserved

Table 2-2. Bit Field Description

Size R/W Reset value

Description

2

R

XX

A port status value.

00: invalid, 10: “0”

01: “1”, 11: “Z”

2

R

XX

B port status value.

00: invalid, 10: “0”

01: “1”, 11: “Z”

1

R

Child node status value.

1: Connected to child node

0: Connected to parent node

1

R

0

Connection status value.

1: Connected

0: Disconnected

1

R

Bias voltage status value.

1: Bias voltage

0: No bias voltage

1 R/W

See

The reset value is set to 0: Enabled.

Description

3

R

Shows the maximum data transfer rate of the node connected to this port.

000: 100 Mbps

001: 200 Mbps

010: 400 Mbps

1 R/W

0

When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias,

Disabled or Fault bits change state.

1 R/W

0

Set to 1 if an error occurs during Suspend/Resume.

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

-

R

000…

Reserved. Read as 0.

16

Preliminary Data Sheet S15306EJ2V0DS

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