UPD72874 データシートの表示（PDF） - NEC => Renesas Technology
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UPD72874 Datasheet PDF : 40 Pages
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µPD72874
Field
Total_ports
Max_speed
Delay
Link_active
Contender
Jitter
Pwr_class
Watchdog
ISBR
Loop
Pwr_fail
Table 2-1. Bit Field Description (2/3)
Size R/W Reset value
Description
4
R
0011
Supported port number.
0011: 3 ports
3
R
010
Indicate the maximum speed that this node supports.
010: 98.304, 196.608 and 393.216 Mbps
4
R
0000
Indicate worst case repeating delay time. 144 + (Delay x 20) = 144 nsec
1 R/W
1
Link active.
1: Enable
0: Disable
The logical AND status of this bit and LPS.
State will be referred to “L bit” of Self-ID Packet#0.
The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It is
an internal signal in the µPD72874.
1 R/W
0
Contender.
“1” indicate this node support bus manager function. This bit will be referred
to “C bit” of Self-ID Packet#0.
3
R
010
The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec
3 R/W
See
Power class.
Description Please refer to IEEE1394a-2000 [4.3.4.1].
This bit will be referred to Pwr field of Self-ID Packet#0.
1 R/W
0
Watchdog Enable.
This bit serves two purposes.
When set to 1, if any one port does resume, the Port_event bit becomes 1.
To determine whether or not an interrupt condition shall be indicated to the
link. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop,
Pwr_fail, Timeout is not output.
1 R/W
0
Initiate short (arbitrated) bus reset.
Setting to 1 acquires the bus and begins short bus reset.
Short bus reset signal output : 1.3 µsec
Returns to 0 at the beginning of the bus reset.
1 R/W
0
Loop detection output.
1: Detection
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
1 R/W
1
Power cable disconnect detect.
It becomes 1 when there is a change from 1 to 0 in the CPS bit.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
14
Preliminary Data Sheet S15306EJ2V0DS
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